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Searched refs:MLXSW_ITEM32 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/net/ethernet/mellanox/mlxsw/
Dcmd.h209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
[all …]
Dreg.h47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
[all …]
Dpci_hw.h74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
[all …]
Dcore_acl_flex_actions.c23 MLXSW_ITEM32(afa, set, type, 0xA0, 28, 4);
28 MLXSW_ITEM32(afa, set, next_action_set_ptr, 0xA4, 0, 24);
35 MLXSW_ITEM32(afa, set, goto_g, 0xA4, 29, 1);
47 MLXSW_ITEM32(afa, set, goto_binding_cmd, 0xA4, 24, 3);
53 MLXSW_ITEM32(afa, set, goto_next_binding, 0xA4, 0, 16);
58 MLXSW_ITEM32(afa, all, action_type, 0x00, 24, 6);
692 MLXSW_ITEM32(afa, vlan, vlan_tag_cmd, 0x00, 29, 3);
695 MLXSW_ITEM32(afa, vlan, vid_cmd, 0x04, 29, 3);
698 MLXSW_ITEM32(afa, vlan, vid, 0x04, 0, 12);
701 MLXSW_ITEM32(afa, vlan, ethertype_cmd, 0x08, 29, 3);
[all …]
Dswitchib.c48 MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
55 MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
60 MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
65 MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
71 MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
81 MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
87 MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
Dswitchx2.c58 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
65 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
70 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
77 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
82 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
92 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
97 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
103 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
108 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
113 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
[all …]
Dcore.c162 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16);
168 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8);
174 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
180 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
186 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
194 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
211 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
216 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16);
221 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
230 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
[all …]
Dspectrum.c82 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
89 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
94 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
99 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
105 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
110 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
116 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
121 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
131 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
138 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
[all …]
Ditem.h348 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ macro