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Searched refs:I915_WRITE (Results 1 – 25 of 42) sorted by relevance

12

/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_vdsc.c512 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); in intel_configure_pps_for_dsc_encoder()
518 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); in intel_configure_pps_for_dsc_encoder()
520 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
522 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), in intel_configure_pps_for_dsc_encoder()
531 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); in intel_configure_pps_for_dsc_encoder()
537 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); in intel_configure_pps_for_dsc_encoder()
539 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
541 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), in intel_configure_pps_for_dsc_encoder()
551 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); in intel_configure_pps_for_dsc_encoder()
557 I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); in intel_configure_pps_for_dsc_encoder()
[all …]
Dintel_color.c144 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]); in ilk_update_pipe_csc()
145 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]); in ilk_update_pipe_csc()
146 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]); in ilk_update_pipe_csc()
148 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]); in ilk_update_pipe_csc()
149 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); in ilk_update_pipe_csc()
151 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]); in ilk_update_pipe_csc()
152 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); in ilk_update_pipe_csc()
154 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]); in ilk_update_pipe_csc()
155 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); in ilk_update_pipe_csc()
158 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]); in ilk_update_pipe_csc()
[all …]
Dvlv_dsi.c104 I915_WRITE(reg, val); in write_data()
165 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
227 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
233 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
333 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
339 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
348 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
383 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
391 I915_WRITE(MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
[all …]
Dicl_dsi.c138 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp); in add_payld_to_queue()
177 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
219 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
226 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
234 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
242 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
250 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
260 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); in dsi_program_swing_and_deemphasis()
295 I915_WRITE(DSS_CTL2, dss_ctl2); in configure_dual_link_mode()
301 I915_WRITE(DSS_CTL1, dss_ctl1); in configure_dual_link_mode()
[all …]
Dintel_combo_phy.c87 I915_WRITE(ICL_PORT_COMP_DW1(phy), val); in cnl_set_procmon_ref_values()
89 I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); in cnl_set_procmon_ref_values()
90 I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); in cnl_set_procmon_ref_values()
156 I915_WRITE(CHICKEN_MISC_2, val); in cnl_combo_phys_init()
163 I915_WRITE(CNL_PORT_COMP_DW0, val); in cnl_combo_phys_init()
167 I915_WRITE(CNL_PORT_CL1CM_DW5, val); in cnl_combo_phys_init()
179 I915_WRITE(CHICKEN_MISC_2, val); in cnl_combo_phys_uninit()
263 I915_WRITE(ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
325 I915_WRITE(ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
333 I915_WRITE(ICL_PORT_COMP_DW8(phy), val); in icl_combo_phys_init()
[all …]
Dintel_fbc.c110 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
140 I915_WRITE(FBC_TAG(i), 0); in i8xx_fbc_activate()
148 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_activate()
149 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); in i8xx_fbc_activate()
160 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_fbc_activate()
181 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); in g4x_fbc_activate()
183 I915_WRITE(DPFC_FENCE_YOFF, 0); in g4x_fbc_activate()
187 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_activate()
198 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
210 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); in intel_fbc_recompress()
[all …]
Dintel_ddi.c944 I915_WRITE(DDI_BUF_TRANS_LO(port, i), in intel_prepare_dp_ddi_buffers()
946 I915_WRITE(DDI_BUF_TRANS_HI(port, i), in intel_prepare_dp_ddi_buffers()
978 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), in intel_prepare_hdmi_ddi_buffers()
980 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), in intel_prepare_hdmi_ddi_buffers()
1085 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1103 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); in hsw_fdi_link_train()
1110 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
1120 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
Dintel_tv.c929 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
940 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1384 I915_WRITE(TV_H_CTL_1, hctl1); in set_tv_mode_timings()
1385 I915_WRITE(TV_H_CTL_2, hctl2); in set_tv_mode_timings()
1386 I915_WRITE(TV_H_CTL_3, hctl3); in set_tv_mode_timings()
1387 I915_WRITE(TV_V_CTL_1, vctl1); in set_tv_mode_timings()
1388 I915_WRITE(TV_V_CTL_2, vctl2); in set_tv_mode_timings()
1389 I915_WRITE(TV_V_CTL_3, vctl3); in set_tv_mode_timings()
1390 I915_WRITE(TV_V_CTL_4, vctl4); in set_tv_mode_timings()
1391 I915_WRITE(TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_audio.c301 I915_WRITE(reg_elda, tmp); in intel_eld_uptodate()
328 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
359 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
364 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); in g4x_audio_codec_enable()
368 I915_WRITE(G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
402 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
415 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
448 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
457 I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
491 I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_audio_codec_disable()
[all …]
Dintel_panel.c609 I915_WRITE(BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
619 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
647 I915_WRITE(BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
658 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
667 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level); in bxt_set_backlight()
748 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in lpt_disable_backlight()
752 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
764 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
767 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
783 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
Dvlv_dsi_pll.c243 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_disable()
348 I915_WRITE(MIPI_CTRL(port), temp | in vlv_dsi_reset_clocks()
396 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); in glk_dsi_program_esc_clock()
397 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); in glk_dsi_program_esc_clock()
451 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
513 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
527 I915_WRITE(BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_enable()
552 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
556 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp); in bxt_dsi_reset_clocks()
560 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp); in bxt_dsi_reset_clocks()
[all …]
Dintel_hdmi.c221 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
224 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
229 I915_WRITE(VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
235 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
253 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_read_infoframe()
294 I915_WRITE(reg, val); in ibx_write_infoframe()
297 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
302 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
308 I915_WRITE(reg, val); in ibx_write_infoframe()
327 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); in ibx_read_infoframe()
[all …]
Dintel_hdcp.c188 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
189 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | in intel_hdcp_clear_keys()
226 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
239 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
247 I915_WRITE(HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
293 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
310 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
327 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
359 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); in intel_hdcp_validate_v_prime()
367 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); in intel_hdcp_validate_v_prime()
[all …]
Dintel_dpll_mgr.c395 I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
396 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
420 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
431 I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
441 I915_WRITE(PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
506 I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
514 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
526 I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
544 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
997 I915_WRITE(DPLL_CTRL1, val); in skl_ddi_pll_write_ctrl1()
[all …]
Dintel_dpio_phy.c283 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
288 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
298 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
303 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
307 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
378 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
399 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
404 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
410 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
415 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
[all …]
Dintel_fifo_underrun.c102 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
121 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()
153 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_check_fifo_underruns()
166 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_set_fifo_underrun_reporting()
219 I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); in cpt_check_pch_fifo_underruns()
234 I915_WRITE(SERR_INT, in cpt_set_fifo_underrun_reporting()
Dintel_psr.c132 I915_WRITE(EDP_PSR_IMR, ~mask); in intel_psr_irq_control()
219 I915_WRITE(PSR_EVENT(cpu_transcoder), val); in intel_psr_irq_handler()
227 I915_WRITE(EDP_PSR_IMR, mask); in intel_psr_irq_handler()
393 I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), in hsw_psr_setup_aux()
404 I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); in hsw_psr_setup_aux()
495 I915_WRITE(EDP_PSR_CTL, val); in hsw_activate_psr1()
531 I915_WRITE(EDP_PSR_CTL, 0); in hsw_activate_psr2()
533 I915_WRITE(EDP_PSR2_CTL, val); in hsw_activate_psr2()
706 I915_WRITE(reg, chicken); in intel_psr_enable_source()
723 I915_WRITE(EDP_PSR_DEBUG, mask); in intel_psr_enable_source()
[all …]
Dintel_display.c496 I915_WRITE(CLKGATE_DIS_PSL(pipe), in skl_wa_827()
500 I915_WRITE(CLKGATE_DIS_PSL(pipe), in skl_wa_827()
511 I915_WRITE(CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
514 I915_WRITE(CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
1381 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1403 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1431 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1459 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); in chv_enable_pll()
1460 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1461 I915_WRITE(CBR4_VLV, 0); in chv_enable_pll()
[all …]
Dintel_cdclk.c512 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | in vlv_program_pfi_credits()
515 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | in vlv_program_pfi_credits()
738 I915_WRITE(LCPLL_CTL, val); in bdw_set_cdclk()
769 I915_WRITE(LCPLL_CTL, val); in bdw_set_cdclk()
773 I915_WRITE(LCPLL_CTL, val); in bdw_set_cdclk()
782 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
967 I915_WRITE(DPLL_CTRL1, val); in skl_dpll0_enable()
970 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); in skl_dpll0_enable()
983 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); in skl_dpll0_disable()
1052 I915_WRITE(CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
[all …]
Dintel_display_power.c408 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); in hsw_power_well_enable()
417 I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val); in hsw_power_well_enable()
439 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); in hsw_power_well_disable()
456 I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); in icl_combo_phy_aux_power_well_enable()
460 I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); in icl_combo_phy_aux_power_well_enable()
476 I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); in icl_combo_phy_aux_power_well_enable()
491 I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); in icl_combo_phy_aux_power_well_disable()
495 I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); in icl_combo_phy_aux_power_well_disable()
594 I915_WRITE(DP_AUX_CH_CTL(aux_ch), val); in icl_tc_phy_aux_power_well_enable()
682 I915_WRITE(DC_STATE_EN, state); in gen9_write_dc_state()
[all …]
Dintel_crt.c187 I915_WRITE(BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
204 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_set_dpms()
444 I915_WRITE(crt->adpa_reg, adpa); in intel_ironlake_crt_detect_hotplug()
453 I915_WRITE(crt->adpa_reg, save_adpa); in intel_ironlake_crt_detect_hotplug()
498 I915_WRITE(crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
503 I915_WRITE(crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
561 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
916 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_reset()
974 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | in intel_crt_init()
978 I915_WRITE(adpa_reg, adpa); in intel_crt_init()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_suspend.c51 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
58 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); in i915_restore_display()
122 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | in i915_restore_state()
126 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); in i915_restore_state()
131 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); in i915_restore_state()
132 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
135 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); in i915_restore_state()
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
141 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); in i915_restore_state()
142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
[all …]
Dintel_pm.c78 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
84 I915_WRITE(CHICKEN_PAR1_1, in gen9_init_clock_gating()
88 I915_WRITE(GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
93 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
98 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
103 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
127 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
136 I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950)); in bxt_init_clock_gating()
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Di915_irq.c276 I915_WRITE(PORT_HOTPLUG_EN, val); in i915_hotplug_interrupt_update_locked()
325 I915_WRITE(DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
399 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u)); in gen6_disable_rps_interrupts()
531 I915_WRITE(GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
563 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
589 I915_WRITE(SDEIMR, sdeimr); in ibx_display_interrupt_update()
653 I915_WRITE(reg, enable_mask | status_mask); in i915_enable_pipestat()
676 I915_WRITE(reg, enable_mask | status_mask); in i915_disable_pipestat()
1298 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivybridge_parity_work()
1317 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); in ivybridge_parity_work()
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Di915_drv.c1406 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY); in i915_driver_register()
2336 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); in vlv_restore_gunit_s0ix_state()
2337 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); in vlv_restore_gunit_s0ix_state()
2338 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); in vlv_restore_gunit_s0ix_state()
2339 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); in vlv_restore_gunit_s0ix_state()
2340 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); in vlv_restore_gunit_s0ix_state()
2343 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); in vlv_restore_gunit_s0ix_state()
2345 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); in vlv_restore_gunit_s0ix_state()
2346 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); in vlv_restore_gunit_s0ix_state()
2348 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); in vlv_restore_gunit_s0ix_state()
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