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Searched refs:I915_READ (Results 1 – 25 of 46) sorted by relevance

12

/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_combo_phy.c51 val = I915_READ(ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
84 val = I915_READ(ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
97 u32 val = I915_READ(reg); in check_phy_reg()
130 return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && in cnl_combo_phy_enabled()
131 (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); in cnl_combo_phy_enabled()
154 val = I915_READ(CHICKEN_MISC_2); in cnl_combo_phys_init()
161 val = I915_READ(CNL_PORT_COMP_DW0); in cnl_combo_phys_init()
165 val = I915_READ(CNL_PORT_CL1CM_DW5); in cnl_combo_phys_init()
177 val = I915_READ(CHICKEN_MISC_2); in cnl_combo_phys_uninit()
187 return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
[all …]
Dicl_dsi.c41 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
48 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
111 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
160 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
214 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); in dsi_program_swing_and_deemphasis()
221 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
228 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); in dsi_program_swing_and_deemphasis()
236 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
244 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
254 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); in dsi_program_swing_and_deemphasis()
[all …]
Dvlv_dsi.c115 u32 val = I915_READ(reg); in read_data()
230 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
332 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
337 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
343 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
344 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
361 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
382 val = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
387 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
388 val = I915_READ(MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_dpll_mgr.c380 val = I915_READ(PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
382 hw_state->fp0 = I915_READ(PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
383 hw_state->fp1 = I915_READ(PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
406 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
525 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
543 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
568 val = I915_READ(WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
588 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
990 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1016 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
[all …]
Dintel_audio.c293 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
299 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
304 if (I915_READ(reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
319 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
326 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
344 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
356 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
366 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
390 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); in hsw_dp_audio_config_update()
404 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); in hsw_dp_audio_config_update()
[all …]
Dintel_ddi.c785 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_hdmi()
806 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_dp()
827 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; in cnl_get_buf_trans_edp()
992 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
1140 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1148 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
1167 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1173 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1235 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()
[all …]
Dintel_display_power.c339 ret = I915_READ(regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
340 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
342 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
343 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
365 wait_for((disabled = !(I915_READ(regs->driver) & in hsw_wait_for_power_well_disable()
407 val = I915_READ(regs->driver); in hsw_power_well_enable()
415 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); in hsw_power_well_enable()
438 val = I915_READ(regs->driver); in hsw_power_well_disable()
455 val = I915_READ(regs->driver); in icl_combo_phy_aux_power_well_enable()
459 val = I915_READ(ICL_PORT_CL_DW12(phy)); in icl_combo_phy_aux_power_well_enable()
[all …]
Dintel_panel.c540 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
547 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
556 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
575 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
591 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
608 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
618 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
646 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
657 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
745 tmp = I915_READ(BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_dpio_phy.c281 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
285 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
290 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
300 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
305 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
317 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
320 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
328 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
340 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
376 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_cdclk.c239 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? in intel_hpll_vco()
409 u32 lcpll = I915_READ(LCPLL_CTL); in hsw_get_cdclk()
414 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
522 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
689 u32 lcpll = I915_READ(LCPLL_CTL); in bdw_get_cdclk()
694 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
721 if (WARN((I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
736 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
744 if (wait_for_us(I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
748 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
[all …]
Dvlv_dsi_pll.c204 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
218 val = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
241 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
328 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
346 temp = I915_READ(MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
415 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
525 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
547 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
554 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
558 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
Dintel_display.c497 I915_READ(CLKGATE_DIS_PSL(pipe)) | in skl_wa_827()
501 I915_READ(CLKGATE_DIS_PSL(pipe)) & in skl_wa_827()
512 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
515 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
1041 line1 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1043 line2 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1095 val = I915_READ(DPLL(pipe)); in assert_pll()
1127 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1130 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1146 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
[all …]
Dintel_lvds.c88 val = I915_READ(lvds_reg); in intel_lvds_port_enabled()
128 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
146 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
159 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
161 val = I915_READ(PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
166 val = I915_READ(PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
170 val = I915_READ(PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
206 val = I915_READ(PP_CONTROL(0)); in intel_lvds_pps_init_hw()
316 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
318 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
Dintel_dvo.c140 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
155 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
171 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
193 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
197 I915_READ(dvo_reg); in intel_disable_dvo()
207 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
214 I915_READ(dvo_reg); in intel_enable_dvo()
289 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
484 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
Dintel_fifo_underrun.c98 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
124 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
146 u32 err_int = I915_READ(GEN7_ERR_INT); in ivybridge_check_fifo_underruns()
176 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
212 u32 serr_int = I915_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
244 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
Dintel_hdmi.c75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
211 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
248 val = I915_READ(VIDEO_DIP_CTL); in g4x_read_infoframe()
256 *data++ = I915_READ(VIDEO_DIP_DATA); in g4x_read_infoframe()
263 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframes_enabled()
284 u32 val = I915_READ(reg); in ibx_write_infoframe()
322 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
330 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
339 u32 val = I915_READ(reg); in ibx_infoframes_enabled()
[all …]
Dintel_crt.c78 val = I915_READ(adpa_reg); in intel_crt_port_enabled()
115 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
437 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
459 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
493 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
507 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
556 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
701 u32 vsync = I915_READ(vsync_reg); in intel_crt_load_detect()
913 adpa = I915_READ(crt->adpa_reg); in intel_crt_reset()
964 adpa = I915_READ(adpa_reg); in intel_crt_init()
[all …]
Dintel_tv.c910 u32 tmp = I915_READ(TV_CTL); in intel_tv_get_hw_state()
929 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
940 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1099 tv_ctl = I915_READ(TV_CTL); in intel_tv_get_config()
1100 hctl1 = I915_READ(TV_H_CTL_1); in intel_tv_get_config()
1101 hctl3 = I915_READ(TV_H_CTL_3); in intel_tv_get_config()
1102 vctl1 = I915_READ(TV_V_CTL_1); in intel_tv_get_config()
1103 vctl2 = I915_READ(TV_V_CTL_2); in intel_tv_get_config()
1138 tmp = I915_READ(TV_WIN_POS); in intel_tv_get_config()
1142 tmp = I915_READ(TV_WIN_SIZE); in intel_tv_get_config()
[all …]
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_suspend.c40 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
44 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
78 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
81 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
86 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
87 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
90 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); in i915_save_state()
93 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
96 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
97 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
[all …]
Di915_debugfs.c395 I915_READ(GEN8_DE_PIPE_IMR(pipe))); in gen8_display_interrupt_info()
398 I915_READ(GEN8_DE_PIPE_IIR(pipe))); in gen8_display_interrupt_info()
401 I915_READ(GEN8_DE_PIPE_IER(pipe))); in gen8_display_interrupt_info()
407 I915_READ(GEN8_DE_PORT_IMR)); in gen8_display_interrupt_info()
409 I915_READ(GEN8_DE_PORT_IIR)); in gen8_display_interrupt_info()
411 I915_READ(GEN8_DE_PORT_IER)); in gen8_display_interrupt_info()
414 I915_READ(GEN8_DE_MISC_IMR)); in gen8_display_interrupt_info()
416 I915_READ(GEN8_DE_MISC_IIR)); in gen8_display_interrupt_info()
418 I915_READ(GEN8_DE_MISC_IER)); in gen8_display_interrupt_info()
421 I915_READ(GEN8_PCU_IMR)); in gen8_display_interrupt_info()
[all …]
Di915_drv.c884 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); in skl_dram_get_channels_info()
889 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); in skl_dram_get_channels_info()
928 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); in skl_get_dram_type()
959 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in skl_get_dram_info()
1063 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0); in bxt_get_dram_info()
1085 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
2251 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
2252 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
2253 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
2254 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
[all …]
Dintel_device_info.c204 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; in gen11_sseu_info_init()
205 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); in gen11_sseu_info_init()
207 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); in gen11_sseu_info_init()
234 const u32 fuse2 = I915_READ(GEN8_FUSE2); in gen10_sseu_info_init()
258 eu_en = ~I915_READ(GEN8_EU_DISABLE0); in gen10_sseu_info_init()
263 eu_en = ~I915_READ(GEN8_EU_DISABLE1); in gen10_sseu_info_init()
270 eu_en = ~I915_READ(GEN8_EU_DISABLE2); in gen10_sseu_info_init()
277 eu_en = ~I915_READ(GEN10_EU_DISABLE3); in gen10_sseu_info_init()
314 fuse = I915_READ(CHV_FUSE_GT); in cherryview_sseu_info_init()
371 fuse2 = I915_READ(GEN8_FUSE2); in gen9_sseu_info_init()
[all …]
Di915_irq.c273 val = I915_READ(PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
375 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
524 old_val = I915_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
578 u32 sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
831 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
1120 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); in vlv_c0_read()
1121 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); in vlv_c0_read()
1297 misccpctl = I915_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1312 error_status = I915_READ(reg); in ivybridge_parity_work()
1618 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
[all …]
Dintel_pm.c79 I915_READ(CHICKEN_PAR1_1) | in gen9_init_clock_gating()
85 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
89 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
93 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
98 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
103 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
127 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
148 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
[all …]
/Linux-v5.4/drivers/gpu/drm/i915/gem/
Di915_gem_stolen.c87 ggtt_start = I915_READ(PGTBL_CTL); in i915_adjust_stolen()
165 u32 reg_val = I915_READ(IS_GM45(dev_priv) ? in g4x_get_stolen_reserved()
196 u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved()
228 u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); in vlv_get_stolen_reserved()
256 u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); in gen7_get_stolen_reserved()
282 u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); in chv_get_stolen_reserved()
314 u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); in bdw_get_stolen_reserved()

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