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Searched refs:GENMASK (Results 1 – 25 of 996) sorted by relevance

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/Linux-v5.4/drivers/net/ethernet/mscc/
Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
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Docelot_qsys.h19 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
20 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
21 #define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
24 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
25 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
26 #define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
38 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
39 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
40 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
41 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
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Docelot_sys.h17 #define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5))
18 #define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5)
19 #define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5)
20 #define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3))
21 #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
22 #define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3)
23 #define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1))
24 #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
25 #define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1)
33 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
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Docelot_dev.h19 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
20 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
35 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
36 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
37 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
38 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
39 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
40 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
41 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
42 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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Docelot_qs.h24 #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
25 #define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
26 #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
34 #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5))
35 #define QS_XTR_CFG_DP_WM_M GENMASK(7, 5)
36 #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5)
37 #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2))
38 #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)
39 #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2)
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0))
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Docelot_rew.h13 #define REW_PORT_VLAN_CFG_PORT_TPID(x) (((x) << 16) & GENMASK(31, 16))
14 #define REW_PORT_VLAN_CFG_PORT_TPID_M GENMASK(31, 16)
15 #define REW_PORT_VLAN_CFG_PORT_TPID_X(x) (((x) & GENMASK(31, 16)) >> 16)
17 #define REW_PORT_VLAN_CFG_PORT_PCP(x) (((x) << 12) & GENMASK(14, 12))
18 #define REW_PORT_VLAN_CFG_PORT_PCP_M GENMASK(14, 12)
19 #define REW_PORT_VLAN_CFG_PORT_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
20 #define REW_PORT_VLAN_CFG_PORT_VID(x) ((x) & GENMASK(11, 0))
21 #define REW_PORT_VLAN_CFG_PORT_VID_M GENMASK(11, 0)
25 #define REW_TAG_CFG_TAG_CFG(x) (((x) << 7) & GENMASK(8, 7))
26 #define REW_TAG_CFG_TAG_CFG_M GENMASK(8, 7)
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/Linux-v5.4/include/soc/mscc/
Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
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/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
57 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
58 #define MT_RXD2_NORMAL_TID GENMASK(11, 8)
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Dregs.h14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
47 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
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/Linux-v5.4/drivers/infiniband/hw/hns/
Dhns_roce_hw_v2.h292 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
303 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
306 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
309 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
312 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
315 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
318 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
321 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
324 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
327 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
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/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
32 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
33 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
37 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
38 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
42 #define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)
43 #define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)
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Dregs.h10 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
16 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
21 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
22 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
37 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
38 #define MT_INT_TX_DONE_ALL GENMASK(7, 4)
46 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
50 #define MT_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
52 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21 GENMASK(23, 22)
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/Linux-v5.4/drivers/media/platform/ti-vpe/
Dcal_regs.h91 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0)
92 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6)
93 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8)
94 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11)
95 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16)
96 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30)
100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
103 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13)
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/Linux-v5.4/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
22 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
54 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
55 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
56 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
71 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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/Linux-v5.4/drivers/mtd/nand/raw/
Ddenali.h24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
27 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
33 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
55 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
67 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
68 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
72 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
73 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
76 #define RE_2_WE__VALUE GENMASK(5, 0)
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/Linux-v5.4/drivers/net/wireless/mediatek/mt7601u/
Dregs.h22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
23 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
25 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
26 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
52 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
53 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
54 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
63 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
66 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
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/Linux-v5.4/drivers/net/ethernet/stmicro/stmmac/
Ddwxgmac2.h18 #define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)
26 #define XGMAC_CONFIG_SARC GENMASK(22, 20)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
35 #define XGMAC_CONFIG_HDSMS GENMASK(14, 12)
66 #define XGMAC_VLAN_VID GENMASK(15, 0)
71 #define XGMAC_VLAN_VLC GENMASK(17, 16)
74 #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
78 #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
89 #define XGMAC_PT GENMASK(31, 16)
124 #define XGMAC_HWFEAT_L3L4FNUM GENMASK(30, 27)
[all …]
Ddwmac4_descs.h19 #define TDES2_BUFFER1_SIZE_MASK GENMASK(13, 0)
20 #define TDES2_VLAN_TAG_MASK GENMASK(15, 14)
22 #define TDES2_BUFFER2_SIZE_MASK GENMASK(29, 16)
24 #define TDES3_IVTIR_MASK GENMASK(19, 18)
28 #define TDES2_IVT_MASK GENMASK(31, 16)
33 #define TDES3_PACKET_SIZE_MASK GENMASK(14, 0)
34 #define TDES3_VLAN_TAG GENMASK(15, 0)
36 #define TDES3_CHECKSUM_INSERTION_MASK GENMASK(17, 16)
38 #define TDES3_TCP_PKT_PAYLOAD_MASK GENMASK(17, 0)
41 #define TDES3_SLOT_NUMBER_MASK GENMASK(22, 19)
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Ddwmac4.h48 #define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
50 #define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
52 #define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
54 #define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
56 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
79 #define GMAC_VLAN_VID GENMASK(15, 0)
82 #define GMAC_VLAN_VLC GENMASK(17, 16)
86 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
94 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
98 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
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/Linux-v5.4/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_err.h56 #define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
57 #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
58 #define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
59 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
60 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
61 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
62 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
67 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
68 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
69 #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
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/Linux-v5.4/include/linux/mfd/syscon/
Datmel-mc.h21 #define AT91_MC_ABTSZ GENMASK(9, 8)
25 #define AT91_MC_ABTTYP GENMASK(11, 10)
35 #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
47 #define AT91_MC_SMC_NWS GENMASK(6, 0)
50 #define AT91_MC_SMC_TDF GENMASK(11, 8)
54 #define AT91_MC_SMC_DBW GENMASK(14, 13)
58 #define AT91_MC_SMC_ACSS GENMASK(17, 16)
61 #define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
63 #define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
69 #define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
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/Linux-v5.4/arch/mips/include/asm/
Dmips-cm.h133 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
134 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
135 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
140 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
148 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
152 #define CM_GCR_REV_MAJOR GENMASK(15, 8)
153 #define CM_GCR_REV_MINOR GENMASK(7, 0)
174 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
176 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
183 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
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/Linux-v5.4/include/linux/mfd/
Dtps68470.h57 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)
58 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
60 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
61 #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)
62 #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)
63 #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)
64 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)
65 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)
67 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
68 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
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/Linux-v5.4/drivers/pci/
Dpci-bridge-emul.c52 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
89 .rw = GENMASK(24, 0),
91 .ro = GENMASK(31, 24),
96 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
101 GENMASK(11, 8) | GENMASK(3, 0)),
110 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
115 .rw = GENMASK(31, 20) | GENMASK(15, 4),
118 .ro = GENMASK(19, 16) | GENMASK(3, 0),
123 .rw = GENMASK(31, 20) | GENMASK(15, 4),
126 .ro = GENMASK(19, 16) | GENMASK(3, 0),
[all …]
/Linux-v5.4/sound/soc/stm/
Dstm32_sai.h39 #define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
44 #define SAI_GCR_SYNCOUT_MASK GENMASK(5, SAI_GCR_SYNCOUT_SHIFT)
53 #define SAI_XCR1_PRTCFG_MASK GENMASK(3, SAI_XCR1_PRTCFG_SHIFT)
57 #define SAI_XCR1_DS_MASK GENMASK(7, SAI_XCR1_DS_SHIFT)
66 #define SAI_XCR1_SYNCEN_MASK GENMASK(11, SAI_XCR1_SYNCEN_SHIFT)
82 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
95 #define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)
108 #define SAI_XCR2_MUTECNT_MASK GENMASK(12, SAI_XCR2_MUTECNT_SHIFT)
115 #define SAI_XCR2_COMP_MASK GENMASK(15, SAI_XCR2_COMP_SHIFT)
120 #define SAI_XFRCR_FRL_MASK GENMASK(7, SAI_XFRCR_FRL_SHIFT)
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