Lines Matching refs:GENMASK
133 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
134 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
135 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
140 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
148 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
152 #define CM_GCR_REV_MAJOR GENMASK(15, 8)
153 #define CM_GCR_REV_MINOR GENMASK(7, 0)
174 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
176 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
183 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
187 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
192 #define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
197 #define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
205 #define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
212 #define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
213 #define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
216 #define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
233 #define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
234 #define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
235 #define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
239 #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
243 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
245 #define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
250 #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
255 #define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
262 #define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
270 #define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
287 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
292 #define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
293 #define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
297 #define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
300 #define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
305 #define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
306 #define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
308 #define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
312 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
316 #define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
317 #define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
323 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
324 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)