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Searched refs:CLK_SDMMC1 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/clk/zte/
Dclk-zx296702.c35 #define CLK_SDMMC1 (lsp0crpm_base + 0x0c) macro
604 ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1); in zx296702_lsp0_clocks_init()
606 zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4); in zx296702_lsp0_clocks_init()
608 zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1); in zx296702_lsp0_clocks_init()
610 zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0); in zx296702_lsp0_clocks_init()
/Linux-v5.4/include/dt-bindings/clock/
Dexynos5250.h84 #define CLK_SDMMC1 281 macro
Dexynos4.h136 #define CLK_SDMMC1 298 macro
Dexynos3250.h204 #define CLK_SDMMC1 198 macro
/Linux-v5.4/drivers/clk/samsung/
Dclk-exynos5250.c562 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
Dclk-exynos3250.c644 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
Dclk-exynos4.c841 GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
/Linux-v5.4/arch/arm/boot/dts/
Dexynos3250.dtsi393 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
Dexynos4.dtsi332 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
Dexynos5250.dtsi555 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;