Home
last modified time | relevance | path

Searched refs:CLK_SDMMC0 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/clk/zte/
Dclk-zx296702.c48 #define CLK_SDMMC0 (lsp1crpm_base + 0x2c) macro
708 ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1); in zx296702_lsp1_clocks_init()
710 zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4); in zx296702_lsp1_clocks_init()
712 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1); in zx296702_lsp1_clocks_init()
714 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0); in zx296702_lsp1_clocks_init()
/Linux-v5.4/include/dt-bindings/clock/
Dexynos5250.h83 #define CLK_SDMMC0 280 macro
Dexynos4.h135 #define CLK_SDMMC0 297 macro
Dexynos3250.h205 #define CLK_SDMMC0 199 macro
/Linux-v5.4/drivers/clk/samsung/
Dclk-exynos5250.c561 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
Dclk-exynos3250.c645 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
Dclk-exynos4.c839 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
/Linux-v5.4/arch/arm/boot/dts/
Dexynos3250.dtsi381 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
Dexynos4.dtsi323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
Dexynos5250.dtsi543 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;