Searched refs:CLK_PDMA0 (Results 1 – 21 of 21) sorted by relevance
| /Linux-v5.4/include/dt-bindings/clock/ |
| D | exynos5410.h | 57 #define CLK_PDMA0 362 macro
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| D | exynos5250.h | 78 #define CLK_PDMA0 275 macro
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| D | s5pv210.h | 115 #define CLK_PDMA0 97 macro
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| D | exynos5420.h | 122 #define CLK_PDMA0 362 macro
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| D | exynos4.h | 130 #define CLK_PDMA0 292 macro
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| D | exynos3250.h | 207 #define CLK_PDMA0 201 macro
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| D | exynos5433.h | 572 #define CLK_PDMA0 65 macro
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| /Linux-v5.4/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 183 GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
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| D | clk-s5pv210.c | 551 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
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| D | clk-exynos5250.c | 556 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
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| D | clk-exynos3250.c | 647 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
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| D | clk-exynos4.c | 835 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
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| D | clk-exynos5420.c | 1028 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
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| D | clk-exynos5433.c | 2328 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | exynos5410.dtsi | 203 clocks = <&clock CLK_PDMA0>;
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| D | s5pv210.dtsi | 142 clocks = <&clocks CLK_PDMA0>;
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| D | exynos3250.dtsi | 433 clocks = <&cmu CLK_PDMA0>;
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| D | exynos4.dtsi | 683 clocks = <&clock CLK_PDMA0>;
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| D | exynos5250.dtsi | 704 clocks = <&clock CLK_PDMA0>;
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| D | exynos5420.dtsi | 385 clocks = <&clock CLK_PDMA0>;
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| /Linux-v5.4/arch/arm64/boot/dts/exynos/ |
| D | exynos5433.dtsi | 1769 clocks = <&cmu_fsys CLK_PDMA0>;
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