Searched refs:CFG_BASE (Results 1 – 4 of 4) sorted by relevance
395 prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; in goya_get_fixed_properties()418 (CFG_BASE - SRAM_BASE_ADDR); in goya_pci_bars_map()772 mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); in goya_init_dma_qman()773 mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); in goya_init_dma_qman()774 so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); in goya_init_dma_qman()775 so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0); in goya_init_dma_qman()778 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()780 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()818 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()820 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()[all …]
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()311 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()380 u64 base_reg = mmPSOC_ETR_BASE - CFG_BASE; in goya_config_etr()473 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()494 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()571 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; in goya_config_spmu()
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
18 #define CFG_BASE 0x7FFC000000ull macro
