Home
last modified time | relevance | path

Searched refs:Base (Results 1 – 25 of 190) sorted by relevance

12345678

/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt42 specific LPC part. Base clocks are numbered from 0 to 27.
45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
46 1 BASE_USB0_CLK Base clock for USB0
47 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
49 3 BASE_USB1_CLK Base clock for USB1
52 5 BASE_SPIFI_CLK Base clock for SPIFI
53 6 BASE_SPI_CLK Base clock for SPI
54 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
55 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
56 9 BASE_APB1_CLK Base clock for APB peripheral block # 1
[all …]
Darmada3700-tbg-clock.txt1 * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
Drenesas,h8300-div-clock.txt11 - reg: Base address and length of the divide rate selector
/Linux-v5.4/Documentation/hwmon/
Dsmsc47b397.rst40 pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
41 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
42 and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
170 Obtaining the HWM Base Address
173 The following is an example of how to read the HWM Base Address located in
191 OUT DX,AL ; Point to HWM Base Addr MSB
193 IN AL,DX ; Get MSB of HWM Base Addr
/Linux-v5.4/arch/arm/boot/dts/
Dspear300.dtsi35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
Dkirkwood-openrd-base.dts3 * Marvell OpenRD Base Board Description
16 model = "OpenRD Base";
Dspear310.dtsi30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
Dspear320.dtsi37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
Darmada-388-clearfog-base.dts3 * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
12 model = "SolidRun Clearfog Base A1";
Dspear600.dtsi77 0xd2000000 0x0010 /* NAND Base DATA */
78 0xd2020000 0x0010 /* NAND Base ADDR */
79 0xd2010000 0x0010>; /* NAND Base CMD */
Dowl-s500-guitar-bb-rev-b.dts12 model = "LeMaker Guitar Base Board rev. B";
Dspear13xx.dtsi140 0xb0800000 0x0010 /* NAND Base DATA */
141 0xb0820000 0x0010 /* NAND Base ADDR */
142 0xb0810000 0x0010>; /* NAND Base CMD */
/Linux-v5.4/Documentation/networking/
Darcnet-hardware.txt568 | Offs|Base |I/O Addr |
593 S1 1-3: I/O Base Address Select
594 4-6: Memory Base Address Select
617 Setting the I/O Base Address
621 of eight possible I/O Base addresses using the following table
637 Setting the Base Memory (RAM) buffer Address
642 Switches 4-6 of switch group S1 select the Base of the 16K block.
801 SW1 1-6: I/O Base Address Select
858 Setting the I/O Base Address
862 of 32 possible I/O Base addresses using the following table
[all …]
Dmultiqueue.txt5 Section 1: Base driver requirements for implementing multiqueue support
12 Section 1: Base driver requirements for implementing multiqueue support
15 Base drivers are required to use the new alloc_etherdev_mq() or
/Linux-v5.4/Documentation/devicetree/bindings/watchdog/
Dsbsa-gwdt.txt1 * SBSA (Server Base System Architecture) Generic Watchdog
6 Base System Architecture (SBSA)
/Linux-v5.4/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
/Linux-v5.4/Documentation/scsi/
Dhptiop.txt64 0x4000 Inbound List Base Address Low
65 0x4004 Inbound List Base Address High
68 0x4050 Outbound List Base Address Low
69 0x4054 Outbound List Base Address High
70 0x4058 Outbound List Copy Pointer Shadow Base Address Low
71 0x405C Outbound List Copy Pointer Shadow Base Address High
/Linux-v5.4/arch/arm/boot/compressed/
Dhead-sharpsl.S29 mov r1, #0x10000000 @ Base address of TC6393 chip
43 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
129 mov r1, #0x0c000000 @ Base address of NAND chip
/Linux-v5.4/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt29 - ranges : Base address and size of the iommu context banks.
39 - reg : Base address and size of context bank within the iommu
44 - reg : Base address and size of the SMMU local base, should
/Linux-v5.4/tools/testing/selftests/rcutorture/bin/
Dconfig_override.sh19 echo Base file $base unreadable!!!
/Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/
Drenesas,h8300-bsc.txt5 - reg: Base address and length of BSC registers.
/Linux-v5.4/arch/arm/
DKconfig-nommu14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
22 hex 'FLASH Base Address' if SET_MEM_PARAM
/Linux-v5.4/Documentation/devicetree/bindings/rng/
Dst,rng.txt6 reg : Base address and size of IP's register map.
/Linux-v5.4/arch/powerpc/boot/dts/fsl/
De500v2_power_isa.dtsi38 power-isa-b; // Base
40 power-isa-atb; // Alternate Time Base
/Linux-v5.4/arch/sh/kernel/cpu/sh2/
Dex.S36 ! Exception Vector Base

12345678