Searched refs:wm_table (Results 1 – 11 of 11) sorted by relevance
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; in dcn3_build_wm_range_table()[all …]
467 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()470 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()471 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()618 static struct wm_table ddr4_wm_table_gs = {655 static struct wm_table lpddr4_wm_table_gs = {692 static struct wm_table lpddr4_wm_table_with_disabled_ppt = {729 static struct wm_table ddr4_wm_table_rn = {766 static struct wm_table ddr4_1R_wm_table_rn = {803 static struct wm_table lpddr4_wm_table_rn = {904 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()[all …]
406 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()409 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()542 static struct wm_table ddr4_wm_table = {579 static struct wm_table lpddr5_wm_table = {671 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()674 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()678 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()679 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()686 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; in vg_clk_mgr_helper_populate_bw_params()[all …]
326 static struct wm_table ddr4_wm_table = {363 static struct wm_table lpddr5_wm_table = {412 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()415 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()601 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()604 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()608 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()609 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()683 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()[all …]
199 struct wm_table { struct215 struct wm_table wm_table; argument
1644 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()1645 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()1646 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()1647 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()1671 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn31_calculate_wm_and_dlg_fp()1676 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()1677 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn31_calculate_wm_and_dlg_fp()1678 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn31_calculate_wm_and_dlg_fp()1697 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn31_calculate_wm_and_dlg_fp()1698 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()[all …]
2144 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg_fp()2149 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg_fp()2150 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()2151 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_calculate_wm_and_dlg_fp()2191 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg_fp()2204 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()2205 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_calculate_wm_and_dlg_fp()2269 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg_fp()2274 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_update_soc_for_wm_a()2275 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_update_soc_for_wm_a()[all …]
1072 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()1079 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()1090 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()1156 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()1164 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()1169 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()1175 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
2530 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local2535 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
3641 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local3646 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
4761 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local4766 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()
