Searched refs:v2_1 (Results 1 – 7 of 7) sorted by relevance
184 const struct rlc_firmware_header_v2_1 *v2_1 = in amdgpu_ucode_print_rlc_hdr() local187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); in amdgpu_ucode_print_rlc_hdr()189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); in amdgpu_ucode_print_rlc_hdr()191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); in amdgpu_ucode_print_rlc_hdr()193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); in amdgpu_ucode_print_rlc_hdr()195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); in amdgpu_ucode_print_rlc_hdr()197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); in amdgpu_ucode_print_rlc_hdr()199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); in amdgpu_ucode_print_rlc_hdr()201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); in amdgpu_ucode_print_rlc_hdr()203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); in amdgpu_ucode_print_rlc_hdr()[all …]
523 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1; member545 args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ in amdgpu_atombios_crtc_set_dce_clock()546 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()547 args.v2_1.asParam.ucDCEClkSrc = clk_src; in amdgpu_atombios_crtc_set_dce_clock()549 ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; in amdgpu_atombios_crtc_set_dce_clock()
241 struct rlc_firmware_header_v2_1 v2_1; member
1405 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member1439 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in amdgpu_atombios_init_mc_reg_table()1442 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in amdgpu_atombios_init_mc_reg_table()
252 const struct smc_firmware_header_v2_1 *v2_1; in smu_v13_0_set_pptable_v2_1() local257 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v13_0_set_pptable_v2_1()259 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v13_0_set_pptable_v2_1()260 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v13_0_set_pptable_v2_1()263 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v13_0_set_pptable_v2_1()
316 const struct smc_firmware_header_v2_1 *v2_1; in smu_v11_0_set_pptable_v2_1() local321 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v11_0_set_pptable_v2_1()323 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v11_0_set_pptable_v2_1()324 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v11_0_set_pptable_v2_1()327 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v11_0_set_pptable_v2_1()
3814 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member3877 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_get_memory_info()3879 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; in radeon_atom_get_memory_info()4002 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_init_mc_reg_table()4005 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in radeon_atom_init_mc_reg_table()
