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Searched refs:uvd (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_uvd.c146 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); in amdgpu_uvd_sw_init()
217 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); in amdgpu_uvd_sw_init()
224 r = amdgpu_ucode_validate(adev->uvd.fw); in amdgpu_uvd_sw_init()
228 release_firmware(adev->uvd.fw); in amdgpu_uvd_sw_init()
229 adev->uvd.fw = NULL; in amdgpu_uvd_sw_init()
234 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()
236 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; in amdgpu_uvd_sw_init()
255 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
257 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_uvd_sw_init()
262 (adev->uvd.fw_version < FW_1_66_16)) in amdgpu_uvd_sw_init()
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Duvd_v7_0.c88 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
122 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
160 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
380 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; in uvd_v7_0_early_init()
381 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in uvd_v7_0_early_init()
384 adev->uvd.harvest_config |= 1 << i; in uvd_v7_0_early_init()
387 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | in uvd_v7_0_early_init()
392 adev->uvd.num_uvd_inst = 1; in uvd_v7_0_early_init()
396 adev->uvd.num_enc_rings = 1; in uvd_v7_0_early_init()
398 adev->uvd.num_enc_rings = 2; in uvd_v7_0_early_init()
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Duvd_v6_0.c67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); in uvd_v6_0_enc_support()
95 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_rptr()
125 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_wptr()
156 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_set_wptr()
369 adev->uvd.num_uvd_inst = 1; in uvd_v6_0_early_init()
378 adev->uvd.num_enc_rings = 2; in uvd_v6_0_early_init()
394 …id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); in uvd_v6_0_sw_init()
400 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { in uvd_v6_0_sw_init()
401 …(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq); in uvd_v6_0_sw_init()
412 for (i = 0; i < adev->uvd.num_enc_rings; ++i) in uvd_v6_0_sw_init()
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Duvd_v3_1.c203 adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs; in uvd_v3_1_set_ring_funcs()
246 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
258 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v3_1_mc_resume()
263 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v3_1_mc_resume()
267 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF; in uvd_v3_1_mc_resume()
285 uint32_t keysel = adev->uvd.keyselect; in uvd_v3_1_fw_validate()
322 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v3_1_start()
517 amdgpu_fence_process(&adev->uvd.inst->ring); in uvd_v3_1_process_interrupt()
529 adev->uvd.inst->irq.num_types = 1; in uvd_v3_1_set_irq_funcs()
530 adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs; in uvd_v3_1_set_irq_funcs()
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Duvd_v4_2.c96 adev->uvd.num_uvd_inst = 1; in uvd_v4_2_early_init()
111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); in uvd_v4_2_sw_init()
119 ring = &adev->uvd.inst->ring; in uvd_v4_2_sw_init()
121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, in uvd_v4_2_sw_init()
159 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_hw_init()
226 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v4_2_hw_fini()
278 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_start()
573 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
585 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
590 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v4_2_mc_resume()
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Duvd_v5_0.c94 adev->uvd.num_uvd_inst = 1; in uvd_v5_0_early_init()
109 …id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); in uvd_v5_0_sw_init()
117 ring = &adev->uvd.inst->ring; in uvd_v5_0_sw_init()
119 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, in uvd_v5_0_sw_init()
155 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_init()
224 cancel_delayed_work_sync(&adev->uvd.idle_work); in uvd_v5_0_hw_fini()
281 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
283 upper_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
297 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
315 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_start()
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Damdgpu_kms.c287 fw_info->ver = adev->uvd.fw_version; in amdgpu_firmware_info()
442 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
443 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
446 if (adev->uvd.inst[i].ring.sched.ready) in amdgpu_hw_ip_info()
462 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
463 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
466 for (j = 0; j < adev->uvd.num_enc_rings; j++) in amdgpu_hw_ip_info()
467 if (adev->uvd.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
476 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
488 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
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Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
Damdgpu_fence.c434 index = ALIGN(adev->uvd.fw->size, 8); in amdgpu_fence_driver_start_ring()
435 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; in amdgpu_fence_driver_start_ring()
436 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; in amdgpu_fence_driver_start_ring()
Damdgpu_virt.c523 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
Damdgpu_ucode.c516 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
Damdgpu.h977 struct amdgpu_uvd uvd; member
/Linux-v5.15/drivers/gpu/drm/radeon/
Dradeon_uvd.c72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
153 rdev->uvd.fw_header_present = true; in radeon_uvd_init()
168 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
188 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
191 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
197 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_init()
199 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
204 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, in radeon_uvd_init()
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Duvd_v4_2.c46 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
74 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
Duvd_v2_2.c113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
Duvd_v1_0.c121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
145 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
Dradeon_drv.c270 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
271 module_param_named(uvd, radeon_uvd, int, 0444);
Dradeon_fence.c849 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index; in radeon_fence_driver_start_ring()
850 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
Dradeon.h2419 struct radeon_uvd uvd; member
/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.h112 uint32_t uvd : 1; member
Dsmu8_hwmgr.h135 uint32_t uvd : 1; member
/Linux-v5.15/drivers/gpu/drm/amd/pm/
Damdgpu_dpm.c1532 adev->uvd.decode_image_width >= WIDTH_4K) { in amdgpu_dpm_enable_uvd()