| /Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv25.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
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| D | nv35.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
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| D | nv36.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
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| D | nv40.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
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| D | nv20.c | 46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
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| D | nv30.c | 52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
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| /Linux-v5.15/drivers/gpu/drm/i915/display/ |
| D | intel_fb.c | 188 unsigned int tiles; in intel_adjust_tile_offset() local
194 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
196 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
197 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
287 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
302 tiles = *x / tile_width; in intel_compute_aligned_offset()
305 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
726 unsigned int tiles; in calc_plane_normal_size() local
733 tiles = DIV_ROUND_UP(size, intel_tile_size(i915)); in calc_plane_normal_size()
735 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * in calc_plane_normal_size()
[all …]
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| /Linux-v5.15/Documentation/admin-guide/perf/ |
| D | thunderx2-pmu.rst | 9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
|
| /Linux-v5.15/drivers/pinctrl/qcom/ |
| D | pinctrl-msm.h | 132 const char *const *tiles; member
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| D | pinctrl-msm.c | 1413 if (soc_data->tiles) { in msm_pinctrl_probe()
1416 soc_data->tiles[i]); in msm_pinctrl_probe()
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| D | pinctrl-sc8180x.c | 1600 .tiles = sc8180x_tiles,
1614 .tiles = sc8180x_tiles,
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| D | pinctrl-sm6115.c | 886 .tiles = sm6115_tiles,
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| D | pinctrl-sc7180.c | 1146 .tiles = sc7180_tiles,
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| D | pinctrl-sdm660.c | 1419 .tiles = sdm660_tiles,
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| D | pinctrl-sm6125.c | 1240 .tiles = sm6125_tiles,
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| /Linux-v5.15/arch/arm/include/debug/ |
| D | vexpress.S | 28 @ - all other (RS1 complaint) tiles use UART mapped
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| /Linux-v5.15/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-reserved.rst | 254 (codenamed sunxi) platforms, with 32x32 tiles for the luminance plane
255 and 32x64 tiles for the chrominance plane. The data in each tile is
260 of tiles, resulting in 32-aligned resolutions for the luminance plane
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| /Linux-v5.15/Documentation/ABI/testing/ |
| D | sysfs-driver-hid-picolcd | 41 tiles get changed and it's not appropriate to expect the application
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| /Linux-v5.15/arch/arm/mach-vexpress/ |
| D | Kconfig | 25 ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
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| /Linux-v5.15/arch/arm/boot/dts/ |
| D | arm-realview-eb.dts | 42 * core tiles.
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| /Linux-v5.15/Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,sm8150-pinctrl.txt | 15 and east TLMM tiles.
|
| D | qcom,qcs404-pinctrl.txt | 15 tiles.
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| D | qcom,sc7180-pinctrl.txt | 15 TLMM tiles
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| D | qcom,sdm660-pinctrl.txt | 16 TLMM tiles.
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| /Linux-v5.15/arch/arm/ |
| D | Kconfig.debug | 1325 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
1332 Note that this will only work with standard A-class core tiles,
1344 bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
1349 of the tiles using the RS1 memory map, including all new A-class
1350 core tiles, FPGA-based SMMs and software models.
1353 bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
1358 Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
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