| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 841 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
876 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1147 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1177 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1190 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1195 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1202 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1226 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1494 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1502 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 787 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
822 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1077 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
1107 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
1120 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1125 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1132 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1156 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1424 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1432 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1255 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1285 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1298 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1303 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1310 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1333 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1349 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1380 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1405 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1505 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1183 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1347 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1377 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1390 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1395 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1402 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1425 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1441 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1475 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1500 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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| D | dcn31_hwseq.c | 168 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn31_init_hw()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable
821 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
951 pool->base.res_cap = &res_cap; in dce60_construct()
959 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
960 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1072 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1145 pool->base.res_cap = &res_cap_61; in dce61_construct()
1269 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1342 pool->base.res_cap = &res_cap_64; in dce64_construct()
1462 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 377 static const struct resource_caps res_cap = { variable
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
956 pool->base.res_cap = &res_cap; in dce80_construct()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
965 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1083 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1355 pool->base.res_cap = &res_cap_83; in dce83_construct()
1477 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_enc_cfg.c | 38 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
121 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
162 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_init()
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| D | dc_resource.c | 305 const struct resource_caps *caps = pool->res_cap; in resource_construct()
2121 return dc->res_pool->res_cap->num_dsc > 0; in dc_resource_is_dsc_encoding_supported()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 376 static const struct resource_caps res_cap = { variable
778 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
990 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1065 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1066 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1121 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1224 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1254 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1267 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1272 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1279 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1302 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1355 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1380 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1663 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1693 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| D | dcn30_hwseq.c | 388 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
418 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
532 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 498 static const struct resource_caps res_cap = { variable
625 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1066 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 930 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
960 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
973 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
978 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
985 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1598 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in update_bw_bounding_box()
1963 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1967 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1978 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
2194 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 549 static const struct resource_caps res_cap = { variable
1011 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1394 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1396 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1410 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1619 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| D | dcn10_hw_sequencer.c | 403 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn10_log_hw_state()
1234 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn10_init_pipes()
1390 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn10_init_hw()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 799 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1227 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1234 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1235 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1368 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1472 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1502 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1515 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1520 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1527 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1682 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1696 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1710 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
3371 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
3394 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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| D | dcn20_hwseq.c | 298 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
307 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
2495 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn20_fpga_init_hw()
2530 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1358 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1365 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1367 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1482 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 286 const struct resource_caps *res_cap; member
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_hw.c | 407 if (line < pool->res_cap->num_ddc) in acquire_i2c_hw_engine()
|
