Searched refs:rd_reg_dword (Results 1 – 16 of 16) sorted by relevance
148 stat = rd_reg_dword(®->host_status); in qla27xx_dump_mpi_ram()159 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()166 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()233 stat = rd_reg_dword(®->host_status); in qla24xx_dump_ram()242 rd_reg_dword(®->hccr); in qla24xx_dump_ram()249 rd_reg_dword(®->hccr); in qla24xx_dump_ram()305 *buf++ = htonl(rd_reg_dword(dmp_reg)); in qla24xx_read_window()317 if (rd_reg_dword(®->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()336 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()341 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()[all …]
685 rd_reg_dword(®->rsp_q_out); in qlafx00_config_rings()914 pseudo_aen = rd_reg_dword(®->pseudoaen); in qlafx00_init_fw_ready()916 aenmbx7 = rd_reg_dword(®->initval7); in qlafx00_init_fw_ready()927 aenmbx = rd_reg_dword(®->aenmailbox0); in qlafx00_init_fw_ready()946 aenmbx7 = rd_reg_dword(®->aenmailbox7); in qlafx00_init_fw_ready()949 ha->req_que_off = rd_reg_dword(®->aenmailbox1); in qlafx00_init_fw_ready()950 ha->rsp_que_off = rd_reg_dword(®->aenmailbox3); in qlafx00_init_fw_ready()951 ha->req_que_len = rd_reg_dword(®->aenmailbox5); in qlafx00_init_fw_ready()952 ha->rsp_que_len = rd_reg_dword(®->aenmailbox6); in qlafx00_init_fw_ready()984 aenmbx7 = rd_reg_dword(®->initval7); in qlafx00_init_fw_ready()[all …]
373 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)383 rd_reg_dword((ha)->cregbase + off)389 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)402 rd_reg_dword((ha)->cregbase + off)
459 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT); in qla2x00_isp_reg_stat()461 return ((rd_reg_dword(®->host_status)) == in qla2x00_isp_reg_stat()472 stat = rd_reg_dword(®->host_status); in qla_pci_disconnected()
461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { in qla24xx_read_flash_dword()462 *data = rd_reg_dword(®->flash_data); in qla24xx_read_flash_dword()505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) in qla24xx_write_flash_dword()1202 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1203 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1245 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1471 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1472 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()1495 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1496 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()481 data = rd_reg_dword(off); in qla82xx_rd_32()898 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_md_rw_32()905 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + in qla82xx_md_rw_32()2025 if (rd_reg_dword(®->host_int)) { in qla82xx_intr_handler()2026 stat = rd_reg_dword(®->host_status); in qla82xx_intr_handler()2091 host_int = rd_reg_dword(®->host_int); in qla82xx_msix_default()2095 stat = rd_reg_dword(®->host_status); in qla82xx_msix_default()2152 host_int = rd_reg_dword(®->host_int); in qla82xx_msix_rsp_q()2186 host_int = rd_reg_dword(®->host_int); in qla82xx_poll()[all …]
466 stat = rd_reg_dword(®->u.isp2300.host_status); in qla2300_intr_handler()3740 rd_reg_dword(rsp->rsp_q_in); in qla_chk_cont_iocb_avail()3953 rd_reg_dword(®->iobase_addr); in qla2xxx_check_risc_status()3955 for (cnt = 10000; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3968 for (cnt = 100; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3980 if (rd_reg_dword(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()3986 rd_reg_dword(®->iobase_window); in qla2xxx_check_risc_status()4030 stat = rd_reg_dword(®->host_status); in qla24xx_intr_handler()4037 hccr = rd_reg_dword(®->hccr); in qla24xx_intr_handler()4159 stat = rd_reg_dword(®->host_status); in qla24xx_msix_default()[all …]
2628 ha->pci_attr = rd_reg_dword(®->ctrl_status); in qla24xx_pci_config()2931 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()2937 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()2942 rd_reg_dword(®->hccr), in qla24xx_reset_risc()2943 rd_reg_dword(®->ctrl_status), in qla24xx_reset_risc()2944 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()2968 rd_reg_dword(®->hccr), in qla24xx_reset_risc()2972 rd_reg_dword(®->ctrl_status); in qla24xx_reset_risc()2975 if ((rd_reg_dword(®->ctrl_status) & in qla24xx_reset_risc()2981 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) in qla24xx_reset_risc()[all …]
311 if (rd_reg_dword(®->isp82.hint) & in qla2x00_mailbox_command()424 ictrl = rd_reg_dword(®->isp24.ictrl); in qla2x00_mailbox_command()425 host_status = rd_reg_dword(®->isp24.host_status); in qla2x00_mailbox_command()426 hccr = rd_reg_dword(®->isp24.hccr); in qla2x00_mailbox_command()584 rd_reg_dword(®->isp24.host_status), in qla2x00_mailbox_command()585 rd_reg_dword(®->isp24.ictrl), in qla2x00_mailbox_command()586 rd_reg_dword(®->isp24.istatus)); in qla2x00_mailbox_command()5513 stat = rd_reg_dword(®->host_status); in qla81xx_write_mpi_register()5524 rd_reg_dword(®->hccr); in qla81xx_write_mpi_register()
2299 cnt = rd_reg_dword(®->isp25mq.req_q_out); in __qla2x00_alloc_iocbs()2301 cnt = rd_reg_dword(reg->isp82.req_q_out); in __qla2x00_alloc_iocbs()2303 cnt = rd_reg_dword(®->isp24.req_q_out); in __qla2x00_alloc_iocbs()2305 cnt = rd_reg_dword(®->ispfx00.req_q_out); in __qla2x00_alloc_iocbs()3600 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
72 value = rd_reg_dword(window); in qla27xx_read32()
3940 if (rd_reg_dword(®->host_int)) { in qla8044_intr_handler()3941 stat = rd_reg_dword(®->host_status); in qla8044_intr_handler()
1980 rd_reg_dword(®->ictrl); in qla24xx_enable_intrs()1995 rd_reg_dword(®->ictrl); in qla24xx_disable_intrs()7709 stat = rd_reg_dword(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()7713 stat = rd_reg_dword(®24->host_status); in qla2xxx_pci_mmio_enabled()
2810 rd_reg_dword(req->req_q_out); in qla28xx_start_scsi_edif()
164 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) in rd_reg_dword() function
6957 rd_reg_dword(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()
