2628 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
2931 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
2937 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
2942 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2943 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
2944 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
2968 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2972 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
2975 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
2981 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
2986 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
2987 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
3007 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3010 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3014 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3038 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3059 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7447 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7449 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()