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Searched refs:pipe_mask (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/
Di915_pci.c160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
181 .pipe_mask = BIT(PIPE_A), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
447 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
502 .pipe_mask = 0, /* legal, last one wins */
511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
608 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dintel_device_info.c329 info->pipe_mask = 0; in intel_device_info_runtime_init()
333 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
340 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
344 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
348 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
354 info->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
Di915_irq.h101 u8 pipe_mask);
103 u8 pipe_mask);
Dintel_device_info.h191 u8 pipe_mask; member
Di915_drv.h1718 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1720 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
Di915_irq.c3187 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument
3202 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
3211 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument
3223 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_ddi.c697 u8 *pipe_mask, bool *is_dp_mst) in intel_ddi_get_encoder_pipes() argument
707 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
729 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
732 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
735 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
773 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
776 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
781 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { in intel_ddi_get_encoder_pipes()
785 *pipe_mask); in intel_ddi_get_encoder_pipes()
786 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
[all …]
Dintel_dpll_mgr.c204 drm_WARN_ON(&dev_priv->drm, !pll->state.pipe_mask); in intel_prepare_shared_dpll()
226 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local
235 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
236 drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
239 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
272 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll() local
282 if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
295 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
326 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
339 shared_dpll[i].pipe_mask, in intel_find_shared_dpll()
[all …]
Dg4x_hdmi.c593 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
595 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
597 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
Dintel_dpll_mgr.h245 u8 pipe_mask; member
Dintel_display_types.h169 u8 pipe_mask; member
1758 INTEL_INFO(i915)->pipe_mask & BIT(pipe) && in intel_pipe_valid()
1773 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); in intel_get_crtc_for_pipe()
Dintel_lvds.c920 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
922 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
Dg4x_dp.c1393 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1395 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1397 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
Dintel_crt.c1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1051 crt->base.pipe_mask = ~0; in intel_crt_init()
Dintel_dvo.c516 intel_encoder->pipe_mask = ~0; in intel_dvo_init()
Dvlv_dsi.c1894 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1896 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1898 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
Dintel_display.c9141 u8 pipe_mask; in verify_single_dpll_state() local
9161 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask, in verify_single_dpll_state()
9163 pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state()
9168 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
9171 I915_STATE_WARN(!(pll->active_mask & pipe_mask), in verify_single_dpll_state()
9175 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_single_dpll_state()
9179 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
9181 pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
9201 u8 pipe_mask = BIT(crtc->pipe); in verify_shared_dpll_state() local
9204 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_shared_dpll_state()
[all …]
Dintel_display.h350 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
Dintel_dp_mst.c909 intel_encoder->pipe_mask = ~0; in intel_dp_create_fake_mst_encoder()
Dintel_tv.c1962 intel_encoder->pipe_mask = ~0; in intel_tv_init()
Dicl_dsi.c2023 encoder->pipe_mask = ~0; in icl_dsi_init()
Dintel_display_debugfs.c1104 pll->state.pipe_mask, pll->active_mask, yesno(pll->on)); in i915_shared_dplls_info()
Dintel_sdvo.c2994 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_setup()
/Linux-v5.15/drivers/usb/renesas_usbhs/
Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
/Linux-v5.15/drivers/staging/media/atomisp/pci/
Dsh_css.c10565 u32 pipe_mask = 0; local
10578 pipe_mask |= (1 << curr_pipe->config.mode);
10582 (((pipe_mask & (1 << IA_CSS_PIPE_MODE_PREVIEW)) ||
10583 (pipe_mask & (1 << IA_CSS_PIPE_MODE_VIDEO))) &&
10584 (pipe_mask & (1 << IA_CSS_PIPE_MODE_CAPTURE)) &&