Searched refs:optimal_dcfclk_for_uclk (Results 1 – 3 of 3) sorted by relevance
1286 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box() local1345 &optimal_dcfclk_for_uclk[i], NULL); in dcn302_update_bw_bounding_box()1346 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn302_update_bw_bounding_box()1347 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_update_bw_bounding_box()1354 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_update_bw_bounding_box()1366 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_update_bw_bounding_box()1370 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_update_bw_bounding_box()1371 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()1385 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_update_bw_bounding_box()1386 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1220 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box() local1277 &optimal_dcfclk_for_uclk[i], NULL); in dcn303_update_bw_bounding_box()1278 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn303_update_bw_bounding_box()1279 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn303_update_bw_bounding_box()1285 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_update_bw_bounding_box()1297 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_update_bw_bounding_box()1301 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_update_bw_bounding_box()1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()1317 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_update_bw_bounding_box()1318 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
2385 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local2445 &optimal_dcfclk_for_uclk[i], NULL); in dcn30_update_bw_bounding_box()2447 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()2448 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()2455 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()2467 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()2471 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2472 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2486 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2487 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
