Searched refs:num_uclk_states (Results 1 – 3 of 3) sorted by relevance
1290 unsigned int num_uclk_states; in dcn302_update_bw_bounding_box() local1340 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_update_bw_bounding_box()1343 for (i = 0; i < num_uclk_states; i++) { in dcn302_update_bw_bounding_box()1353 for (j = 0; j < num_uclk_states; j++) { in dcn302_update_bw_bounding_box()1365 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()1370 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_update_bw_bounding_box()1374 j = num_uclk_states; in dcn302_update_bw_bounding_box()1384 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_update_bw_bounding_box()
1224 unsigned int num_uclk_states; in dcn303_update_bw_bounding_box() local1272 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_update_bw_bounding_box()1275 for (i = 0; i < num_uclk_states; i++) { in dcn303_update_bw_bounding_box()1284 for (j = 0; j < num_uclk_states; j++) { in dcn303_update_bw_bounding_box()1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()1301 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_update_bw_bounding_box()1306 j = num_uclk_states; in dcn303_update_bw_bounding_box()1316 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_update_bw_bounding_box()
2389 unsigned int num_uclk_states; in dcn30_update_bw_bounding_box() local2439 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()2442 for (i = 0; i < num_uclk_states; i++) { in dcn30_update_bw_bounding_box()2454 for (j = 0; j < num_uclk_states; j++) { in dcn30_update_bw_bounding_box()2466 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2471 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2475 j = num_uclk_states; in dcn30_update_bw_bounding_box()2485 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
