Searched refs:iommu_virt_to_phys (Results 1 – 4 of 4) sorted by relevance
93 static inline u64 iommu_virt_to_phys(void *vaddr) in iommu_virt_to_phys() function
198 *pte = PM_LEVEL_PDE(domain->iop.mode, iommu_virt_to_phys(domain->iop.root)); in increase_address_space()284 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); in alloc_pte()
394 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()422 entry = iommu_virt_to_phys(amd_iommu_dev_table); in iommu_set_device_table()683 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()736 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()777 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()850 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_init_ga_log()853 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_init_ga_log()
844 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); in build_completion_wait()1444 pte_root = iommu_virt_to_phys(domain->iop.root); in set_dte_entry()1463 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); in set_dte_entry()2473 *pte = iommu_virt_to_phys(root) | GCR3_VALID; in __get_gcr3_pte()2622 dte |= iommu_virt_to_phys(table->table); in set_dte_irq_entry()
