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Searched refs:intel_de_write (Results 1 – 25 of 43) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_vdsc.c605 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
612 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
615 intel_de_write(dev_priv, in intel_dsc_pps_configure()
619 intel_de_write(dev_priv, in intel_dsc_pps_configure()
629 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
636 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
639 intel_de_write(dev_priv, in intel_dsc_pps_configure()
643 intel_de_write(dev_priv, in intel_dsc_pps_configure()
654 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
661 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
[all …]
Dintel_fdi.c166 intel_de_write(dev_priv, reg, temp); in intel_fdi_normal_train()
177 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); in intel_fdi_normal_train()
185 intel_de_write(dev_priv, reg, in intel_fdi_normal_train()
208 intel_de_write(dev_priv, reg, temp); in ilk_fdi_link_train()
219 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); in ilk_fdi_link_train()
225 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); in ilk_fdi_link_train()
231 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
233 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), in ilk_fdi_link_train()
243 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); in ilk_fdi_link_train()
255 intel_de_write(dev_priv, reg, temp); in ilk_fdi_link_train()
[all …]
Dvlv_dsi.c106 intel_de_write(dev_priv, reg, val); in write_data()
168 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
178 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
234 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
241 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
341 intel_de_write(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
348 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
357 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
392 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in glk_dsi_device_ready()
401 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
[all …]
Dintel_color.c161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); in ilk_update_pipe_csc()
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); in ilk_update_pipe_csc()
163 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); in ilk_update_pipe_csc()
165 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
167 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); in ilk_update_pipe_csc()
169 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
171 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); in ilk_update_pipe_csc()
173 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
175 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); in ilk_update_pipe_csc()
178 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), in ilk_update_pipe_csc()
[all …]
Dicl_dsi.c145 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); in add_payld_to_queue()
185 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
235 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp); in icl_dsi_frame_update()
256 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
263 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
271 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
279 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
287 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
298 intel_de_write(dev_priv, in dsi_program_swing_and_deemphasis()
335 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); in configure_dual_link_mode()
[all …]
Dintel_combo_phy.c83 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in icl_set_procmon_ref_values()
85 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
86 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
305 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
342 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
350 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
355 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
363 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); in icl_combo_phys_init()
368 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_init()
372 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); in icl_combo_phys_init()
[all …]
Dintel_tv.c930 intel_de_write(dev_priv, TV_CTL, in intel_enable_tv()
943 intel_de_write(dev_priv, TV_CTL, in intel_disable_tv()
1385 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); in set_tv_mode_timings()
1386 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); in set_tv_mode_timings()
1387 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); in set_tv_mode_timings()
1388 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); in set_tv_mode_timings()
1389 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); in set_tv_mode_timings()
1390 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); in set_tv_mode_timings()
1391 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); in set_tv_mode_timings()
1392 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
Dintel_vrr.c176 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); in intel_vrr_enable()
177 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); in intel_vrr_enable()
178 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl); in intel_vrr_enable()
179 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); in intel_vrr_enable()
180 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); in intel_vrr_enable()
192 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), in intel_vrr_send_push()
205 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); in intel_vrr_disable()
206 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); in intel_vrr_disable()
Dg4x_hdmi.c55 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); in intel_hdmi_prepare()
174 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in g4x_enable_hdmi()
201 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
203 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
215 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, in ibx_enable_hdmi()
223 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
225 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
262 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
269 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
276 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
[all …]
Dintel_audio.c314 intel_de_write(dev_priv, reg_elda, tmp); in intel_eld_uptodate()
341 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
373 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
378 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, in g4x_audio_codec_enable()
383 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
418 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
431 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
464 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
473 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
507 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_audio_codec_disable()
[all …]
Dintel_fbc.c90 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
120 intel_de_write(dev_priv, FBC_TAG(i), 0); in i8xx_fbc_activate()
130 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_activate()
131 intel_de_write(dev_priv, FBC_FENCE_OFF, in i8xx_fbc_activate()
143 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_activate()
183 intel_de_write(dev_priv, DPFC_FENCE_YOFF, in g4x_fbc_activate()
186 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0); in g4x_fbc_activate()
190 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_activate()
201 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
239 intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); in snb_fbc_recompress()
[all …]
Dintel_panel.c641 intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
651 intel_de_write(dev_priv, BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
679 intel_de_write(dev_priv, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
690 intel_de_write(dev_priv, VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
699 intel_de_write(dev_priv, in bxt_set_backlight()
782 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, in lpt_disable_backlight()
787 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
799 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
802 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
818 intel_de_write(dev_priv, BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
Dvlv_dsi_pll.c246 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_disable()
352 intel_de_write(dev_priv, MIPI_CTRL(port), in vlv_dsi_reset_clocks()
399 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
401 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
456 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
519 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
533 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_enable()
559 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
563 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); in bxt_dsi_reset_clocks()
567 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); in bxt_dsi_reset_clocks()
[all …]
Dintel_fifo_underrun.c103 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
122 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
156 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
169 intel_de_write(dev_priv, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
209 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), in bdw_set_fifo_underrun_reporting()
243 intel_de_write(dev_priv, SERR_INT, in cpt_check_pch_fifo_underruns()
259 intel_de_write(dev_priv, SERR_INT, in cpt_set_fifo_underrun_reporting()
420 intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns); in intel_cpu_fifo_underrun_irq_handler()
Dintel_ddi.c118 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
120 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), in hsw_prepare_dp_ddi_buffers()
152 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), in hsw_prepare_hdmi_ddi_buffers()
154 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), in hsw_prepare_hdmi_ddi_buffers()
399 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); in intel_ddi_set_dp_msa()
541 intel_de_write(dev_priv, in intel_ddi_enable_transcoder_func()
545 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), in intel_ddi_enable_transcoder_func()
565 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); in intel_ddi_config_transcoder_func()
576 intel_de_write(dev_priv, in intel_ddi_disable_transcoder_func()
598 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); in intel_ddi_disable_transcoder_func()
[all …]
Dintel_dsb.c56 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); in intel_dsb_enable_engine()
74 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); in intel_dsb_disable_engine()
103 intel_de_write(dev_priv, reg, val); in intel_dsb_indexed_reg_write()
180 intel_de_write(dev_priv, reg, val); in intel_dsb_reg_write()
224 intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), in intel_dsb_commit()
240 intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), in intel_dsb_commit()
Dintel_dpll_mgr.c459 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
460 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
484 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
495 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
505 intel_de_write(dev_priv, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
585 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
593 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
605 intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
623 intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
1205 intel_de_write(dev_priv, DPLL_CTRL1, val); in skl_ddi_pll_write_ctrl1()
[all …]
Dintel_pps.c105 intel_de_write(dev_priv, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
108 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
111 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
608 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
674 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
786 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
794 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
802 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
847 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
891 intel_de_write(dev_priv, pp_ctrl_reg, pp); in intel_pps_backlight_on()
[all …]
Dintel_dpio_phy.c285 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
290 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
301 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
306 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
310 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
383 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
405 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
410 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
416 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
421 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
[all …]
Dintel_hdcp.c265 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
266 intel_de_write(dev_priv, HDCP_KEY_STATUS, in intel_hdcp_clear_keys()
305 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
318 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
326 intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
393 intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
410 intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
429 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
462 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
471 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
[all …]
Dintel_hdmi.c213 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
216 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
221 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
227 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
245 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_read_infoframe()
287 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
290 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
296 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
302 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
321 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); in ibx_read_infoframe()
[all …]
Dintel_snps_phy.c103 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), in intel_snps_phy_ddi_vswing_sequence()
701 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); in intel_mpllb_enable()
702 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); in intel_mpllb_enable()
703 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); in intel_mpllb_enable()
704 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); in intel_mpllb_enable()
705 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); in intel_mpllb_enable()
706 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); in intel_mpllb_enable()
707 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); in intel_mpllb_enable()
727 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), in intel_mpllb_enable()
Dg4x_dp.c163 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); in intel_dp_prepare()
228 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_on()
243 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_on()
262 intel_de_write(dev_priv, DP_A, intel_dp->DP); in ilk_edp_pll_off()
446 intel_de_write(dev_priv, intel_dp->output_reg, DP); in intel_dp_link_down()
450 intel_de_write(dev_priv, intel_dp->output_reg, DP); in intel_dp_link_down()
470 intel_de_write(dev_priv, intel_dp->output_reg, DP); in intel_dp_link_down()
474 intel_de_write(dev_priv, intel_dp->output_reg, DP); in intel_dp_link_down()
604 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in cpt_set_link_train()
633 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); in g4x_set_link_train()
[all …]
Dintel_dvo.c198 intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
216 intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
305 intel_de_write(dev_priv, dvo_srcdim_reg, in intel_dvo_pre_enable()
307 intel_de_write(dev_priv, dvo_reg, dvo_val); in intel_dvo_pre_enable()
492 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
500 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_suspend.c68 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); in intel_restore_swf()
69 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
72 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); in intel_restore_swf()
75 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
78 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); in intel_restore_swf()
79 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); in intel_restore_swf()
82 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); in intel_restore_swf()
119 intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()

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