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Searched refs:intel_de_read (Results 1 – 25 of 51) sorted by relevance

123

/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_fdi.c158 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
169 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
186 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); in intel_fdi_normal_train()
205 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
209 intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
214 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
222 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
238 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
252 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
258 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
[all …]
Dintel_combo_phy.c47 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
80 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
93 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
151 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
153 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
155 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
302 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
333 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
346 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy)); in icl_combo_phys_init()
352 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); in icl_combo_phys_init()
[all …]
Dicl_dsi.c46 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
53 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
117 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
168 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
233 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port)); in icl_dsi_frame_update()
251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); in dsi_program_swing_and_deemphasis()
258 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
265 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); in dsi_program_swing_and_deemphasis()
273 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
281 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
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Dintel_dpll_mgr.c444 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
446 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
447 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
470 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
604 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
622 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
647 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
667 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1092 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1198 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
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Dvlv_dsi.c117 u32 val = intel_de_read(dev_priv, reg); in read_data()
237 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
340 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
346 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
352 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); in glk_dsi_enable_io()
353 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
370 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
391 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
397 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
398 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_audio.c306 tmp = intel_de_read(dev_priv, reg_eldv); in intel_eld_uptodate()
312 tmp = intel_de_read(dev_priv, reg_elda); in intel_eld_uptodate()
317 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) in intel_eld_uptodate()
332 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_disable()
339 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
358 tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); in g4x_audio_codec_enable()
370 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
381 tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
406 tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); in hsw_dp_audio_config_update()
420 tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); in hsw_dp_audio_config_update()
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Dintel_pps.c57 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
71 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
81 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
237 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
243 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
260 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
413 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
426 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
440 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
441 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); in intel_pps_check_power_unlocked()
[all …]
Dintel_panel.c577 return intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
584 return intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
593 val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
614 return intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in vlv_get_backlight()
622 return intel_de_read(dev_priv, in bxt_get_backlight()
640 u32 val = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
650 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
678 tmp = intel_de_read(dev_priv, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
689 tmp = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
778 tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_dpio_phy.c283 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
287 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
292 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
308 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
320 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
323 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
331 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
343 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
381 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_ddi.c166 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
183 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_active()
298 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()
579 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_disable_transcoder_func()
624 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_toggle_hdcp_bits()
662 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_connector_get_hw_state()
715 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
720 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
761 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
799 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); in intel_ddi_get_encoder_pipes()
[all …]
Dvlv_dsi_pll.c205 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
219 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
244 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_disable()
332 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
350 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
420 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
531 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_enable()
554 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
561 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); in bxt_dsi_reset_clocks()
565 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); in bxt_dsi_reset_clocks()
Dintel_lvds.c88 val = intel_de_read(dev_priv, lvds_reg); in intel_lvds_port_enabled()
128 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
146 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
159 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
161 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
166 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
170 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
207 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
316 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
319 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
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Dintel_dvo.c141 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
156 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
172 tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
195 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
199 intel_de_read(dev_priv, dvo_reg); in intel_disable_dvo()
210 u32 temp = intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
217 intel_de_read(dev_priv, dvo_reg); in intel_enable_dvo()
293 dvo_val = intel_de_read(dev_priv, dvo_reg) & in intel_dvo_pre_enable()
491 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
Dintel_display_power.c377 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
378 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
380 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
381 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
403 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & in hsw_wait_for_power_well_disable()
447 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enable()
476 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_disable()
493 val = intel_de_read(dev_priv, regs->driver); in icl_combo_phy_aux_power_well_enable()
498 val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); in icl_combo_phy_aux_power_well_enable()
508 val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)); in icl_combo_phy_aux_power_well_enable()
[all …]
Dintel_fifo_underrun.c99 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
126 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
149 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
180 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
236 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
269 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
418 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & in intel_cpu_fifo_underrun_irq_handler()
Dintel_display.c368 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); in skl_wa_827()
371 … intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); in skl_wa_827()
381 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
384 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
418 line1 = intel_de_read(dev_priv, reg) & line_mask; in pipe_scanline_is_moving()
420 line2 = intel_de_read(dev_priv, reg) & line_mask; in pipe_scanline_is_moving()
474 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
510 u32 val = intel_de_read(dev_priv, in assert_fdi_tx()
514 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); in assert_fdi_tx()
530 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); in assert_fdi_rx()
[all …]
Dg4x_dp.c134 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
158 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); in intel_dp_prepare()
188 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; in assert_dp_port()
199 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
273 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
297 val = intel_de_read(dev_priv, dp_reg); in g4x_dp_port_enabled()
349 tmp = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_get_config()
354 u32 trans_dp = intel_de_read(dev_priv, in intel_dp_get_config()
389 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) in intel_dp_get_config()
432 (intel_de_read(dev_priv, intel_dp->output_reg) & in intel_dp_link_down()
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Dintel_tv.c910 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
931 intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
944 intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1099 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1100 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1101 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1102 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1103 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1138 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1142 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
[all …]
Dintel_crt.c81 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
118 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
466 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
490 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
525 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
541 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
592 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
741 u32 vsync = intel_de_read(dev_priv, vsync_reg); in intel_crt_load_detect()
958 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
1009 adpa = intel_de_read(dev_priv, adpa_reg); in intel_crt_init()
[all …]
Dintel_hdmi.c71 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
80 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
202 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
240 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_read_infoframe()
248 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); in g4x_read_infoframe()
255 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
276 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
316 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); in ibx_read_infoframe()
324 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
333 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
[all …]
Dintel_vrr.c216 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); in intel_vrr_get_config()
229 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; in intel_vrr_get_config()
230 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; in intel_vrr_get_config()
231 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; in intel_vrr_get_config()
Dintel_overlay.c328 tmp = intel_de_read(dev_priv, DOVSTA); in intel_overlay_continue()
462 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { in intel_overlay_release_old_vid()
936 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); in update_pfit_vscale_ratio()
944 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; in update_pfit_vscale_ratio()
947 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
949 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1285 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); in intel_overlay_attrs_ioctl()
1286 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); in intel_overlay_attrs_ioctl()
1287 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); in intel_overlay_attrs_ioctl()
1288 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); in intel_overlay_attrs_ioctl()
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Dintel_cdclk.c245 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
420 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
425 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
534 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
704 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
709 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
753 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
776 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
786 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
842 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
[all …]
Dintel_snps_phy.c825 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); in intel_mpllb_readout_hw_state()
826 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); in intel_mpllb_readout_hw_state()
827 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); in intel_mpllb_readout_hw_state()
828 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); in intel_mpllb_readout_hw_state()
829 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); in intel_mpllb_readout_hw_state()
830 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); in intel_mpllb_readout_hw_state()
831 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); in intel_mpllb_readout_hw_state()
839 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & in intel_mpllb_readout_hw_state()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()

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