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Searched refs:intel_de_posting_read (Results 1 – 25 of 27) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_fdi.c180 intel_de_posting_read(dev_priv, reg); in intel_fdi_normal_train()
227 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
263 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
310 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
339 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
349 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
394 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
404 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
447 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
489 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
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Dg4x_hdmi.c56 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
175 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in g4x_enable_hdmi()
202 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
204 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
217 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
224 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
226 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
270 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
277 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
311 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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Dg4x_dp.c229 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
244 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_on()
263 intel_de_posting_read(dev_priv, DP_A); in ilk_edp_pll_off()
447 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
451 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
471 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
475 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_link_down()
605 intel_de_posting_read(dev_priv, intel_dp->output_reg); in cpt_set_link_train()
634 intel_de_posting_read(dev_priv, intel_dp->output_reg); in g4x_set_link_train()
658 intel_de_posting_read(dev_priv, intel_dp->output_reg); in intel_dp_enable_port()
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Dintel_pps.c106 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
109 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
112 intel_de_posting_read(dev_priv, intel_dp->output_reg); in vlv_power_sequencer_kick()
609 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
675 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
787 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
795 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
803 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_on_unlocked()
848 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_off_unlocked()
892 intel_de_posting_read(dev_priv, pp_ctrl_reg); in intel_pps_backlight_on()
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Dintel_fifo_underrun.c104 intel_de_posting_read(dev_priv, reg); in i9xx_check_fifo_underruns()
124 intel_de_posting_read(dev_priv, reg); in i9xx_set_fifo_underrun_reporting()
157 intel_de_posting_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
245 intel_de_posting_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
Dintel_hdmi.c228 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
303 intel_de_posting_read(dev_priv, reg); in ibx_write_infoframe()
385 intel_de_posting_read(dev_priv, reg); in cpt_write_infoframe()
461 intel_de_posting_read(dev_priv, reg); in vlv_write_infoframe()
543 intel_de_posting_read(dev_priv, ctl_reg); in hsw_write_infoframe()
891 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
911 intel_de_posting_read(dev_priv, reg); in g4x_set_infoframes()
1063 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1084 intel_de_posting_read(dev_priv, reg); in ibx_set_infoframes()
1120 intel_de_posting_read(dev_priv, reg); in cpt_set_infoframes()
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Dintel_dsb.c58 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_enable_engine()
76 intel_de_posting_read(i915, DSB_CTRL(pipe, id)); in intel_dsb_disable_engine()
Dintel_pipe_crc.c620 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_set_crc_source()
655 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_enable_pipe_crc()
670 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); in intel_crtc_disable_pipe_crc()
Dintel_de.h21 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read() function
Dintel_vga.c44 intel_de_posting_read(dev_priv, vga_reg); in intel_vga_disable()
Dintel_dpll.c1399 intel_de_posting_read(dev_priv, reg); in i9xx_enable_pll()
1417 intel_de_posting_read(dev_priv, reg); in i9xx_enable_pll()
1458 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1481 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in vlv_enable_pll()
1552 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); in chv_enable_pll()
1812 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1829 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
1855 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
Dintel_dpll_mgr.c487 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
496 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_enable()
506 intel_de_posting_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_disable()
586 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
594 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_enable()
606 intel_de_posting_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
624 intel_de_posting_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_disable()
1206 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1219 intel_de_posting_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_enable()
1220 intel_de_posting_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_enable()
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Dintel_panel.c954 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
990 intel_de_posting_read(dev_priv, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
1004 intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
1034 intel_de_posting_read(dev_priv, BLC_PWM_CTL); in i9xx_enable_backlight()
1077 intel_de_posting_read(dev_priv, BLC_PWM_CTL2); in i965_enable_backlight()
1109 intel_de_posting_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
1162 intel_de_posting_read(dev_priv, in bxt_enable_backlight()
1198 intel_de_posting_read(dev_priv, in cnp_enable_backlight()
Dintel_lvds.c320 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
345 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
Dintel_crt.c485 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
962 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
Dicl_dsi.c383 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
389 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
396 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
721 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
Dvlv_dsi_pll.c520 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
Dintel_dmc.c270 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); in gen9_set_dc_state_debugmask()
Dintel_ddi.c1445 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2234 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_disable_fec_state()
3094 intel_de_posting_read(dev_priv, reg); in intel_enable_ddi_hdmi()
3329 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3344 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3348 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
Dintel_sdvo.c224 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
231 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
248 intel_de_posting_read(dev_priv, GEN3_SDVOB); in intel_sdvo_write_sdvox()
251 intel_de_posting_read(dev_priv, GEN3_SDVOC); in intel_sdvo_write_sdvox()
Dintel_display.c993 intel_de_posting_read(dev_priv, reg); in intel_enable_pipe()
2474 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
2742 intel_de_posting_read(dev_priv, IPS_CTL); in hsw_disable_ips()
4985 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_set_pipeconf()
5365 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
5382 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
5393 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
5407 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
5806 intel_de_posting_read(dev_priv, PIPECONF(pipe)); in ilk_set_pipeconf()
5829 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); in hsw_set_pipeconf()
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Dintel_tv.c1619 intel_de_posting_read(dev_priv, TV_DAC); in intel_tv_detect_type()
1651 intel_de_posting_read(dev_priv, TV_CTL); in intel_tv_detect_type()
Dintel_cdclk.c980 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1076 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1091 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
Dvlv_dsi.c696 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
715 intel_de_posting_read(dev_priv, port_ctrl); in intel_dsi_port_disable()
Dintel_display_power.c5200 intel_de_posting_read(dev_priv, reg); in gen9_dbuf_slice_set()
5377 intel_de_posting_read(dev_priv, D_COMP_BDW); in hsw_write_dcomp()
5411 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
5429 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
5456 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()

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