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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 44) sorted by relevance

12

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dinterrupt.c154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
332 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
334 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
361 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
367 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
369 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
415 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
473 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
484 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
490 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
Dedid.c381 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
383 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
411 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
413 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
Dscheduler.c90 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
91 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
92 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
112 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
272 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
276 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
[all …]
Dmmio_context.c225 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
255 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
282 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
538 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
Dgvt.h452 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
456 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
Dhandlers.c170 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
173 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
782 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { in force_nonpriv_write()
800 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
882 end = i915_mmio_reg_offset(i915_end); in calc_index()
1077 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) in trigger_aux_channel_interrupt()
1080 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
1083 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
1086 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
1957 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || in mmio_read_from_hw()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dselftest_lrc.c265 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
270 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
275 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
280 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
285 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
290 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
295 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
300 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
305 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
310 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
[all …]
Dintel_lrc.c1018 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1026 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1027 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1032 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1033 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1046 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_restore_scratch()
1062 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1070 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1071 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1287 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
[all …]
Dintel_workarounds.c86 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
114 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
116 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
123 i915_mmio_reg_offset(wa_->reg), in _wa_add()
142 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
143 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
144 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
145 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
717 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1235 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
[all …]
Dselftest_workarounds.c160 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
187 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
468 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
523 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
881 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
917 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
976 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
980 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
1004 i915_mmio_reg_offset(reg), a, b); in result_eq()
1026 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
Dintel_ring_submission.c652 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
656 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
661 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
666 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
714 *cs++ = i915_mmio_reg_offset( in mi_set_context()
769 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
776 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
811 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
Dselftest_rps.c99 *cs++ = i915_mmio_reg_offset(CS_GPR(i)); in create_spin_counter()
101 *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4; in create_spin_counter()
106 *cs++ = i915_mmio_reg_offset(CS_GPR(INC)); in create_spin_counter()
121 *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); in create_spin_counter()
204 i915_mmio_reg_offset(BXT_RP_STATE_CAP), in show_pstate_limits()
209 i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS), in show_pstate_limits()
Dselftest_mocs.c150 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in read_l3cc_table()
195 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in check_l3cc_table()
Dgen7_renderclear.c399 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); in emit_batch()
404 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
Dgen8_engine_cs.c194 *cs++ = i915_mmio_reg_offset(inv_reg); in gen12_emit_aux_table_inv()
318 *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine)); in gen12_emit_flush_xcs()
Dselftest_rc6.c147 *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO); in __live_rc6_ctx()
Dintel_rc6.c747 i = (i915_mmio_reg_offset(reg) - in intel_rc6_residency_ns()
748 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); in intel_rc6_residency_ns()
Dselftest_engine_pm.c58 *cs++ = i915_mmio_reg_offset(reg); in emit_srm()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_dsb.c129 if (reg_val != i915_mmio_reg_offset(reg)) { in intel_dsb_indexed_reg_write()
141 i915_mmio_reg_offset(reg); in intel_dsb_indexed_reg_write()
194 i915_mmio_reg_offset(reg); in intel_dsb_reg_write()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_uncore.h288 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
295 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
437 readl(base + i915_mmio_reg_offset(reg))
439 writel(value, base + i915_mmio_reg_offset(reg))
Di915_perf.c1618 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
1697 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4; in alloc_noa_wait()
1700 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1701 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
1715 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
1718 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1719 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
1738 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE)); in alloc_noa_wait()
1739 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1); in alloc_noa_wait()
1757 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)); in alloc_noa_wait()
[all …]
Dintel_uncore.c1042 u32 offset = i915_mmio_reg_offset(*reg); in mmio_reg_cmp()
1505 i915_mmio_reg_offset(reg))) in __unclaimed_reg_debug()
1584 u32 offset = i915_mmio_reg_offset(reg); \
1639 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1693 u32 offset = i915_mmio_reg_offset(reg); \
1732 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1808 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); in __fw_domain_init()
1809 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); in __fw_domain_init()
2310 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_uc.c400 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET), in uc_init_wopcm()
403 i915_mmio_reg_offset(GUC_WOPCM_SIZE), in uc_init_wopcm()
Dintel_guc.c172 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); in intel_guc_init_early()
180 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); in intel_guc_init_early()
/Linux-v5.15/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c80 u32 offset = i915_mmio_reg_offset(*reg); in intel_shadow_table_check()

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