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Searched refs:hwirq (Results 1 – 25 of 354) sorted by relevance

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/Linux-v5.15/Documentation/translations/zh_CN/core-api/irq/
Dirq-domain.rst32 提供任何对控制器本地IRQ(hwirq)号到Linux IRQ号空间的反向映射的支持。
34 irq_domain 库在 irq_alloc_desc*() API 的基础上增加了 hwirq 和 IRQ 号码
38 irq_domain还实现了从抽象的irq_fwspec结构体到hwirq号的转换（到目前为止是
49 在大多数情况下，irq_domain在开始时是空的，没有任何hwirq和IRQ号之间的映射。
51 irq_domain和一个hwirq号作为参数。 如果hwirq的映射还不存在，那么它将分配
52 一个新的Linux irq_desc，将其与hwirq关联起来，并调用.map()回调，这样驱动
55 当接收到一个中断时，应该使用irq_find_mapping()函数从hwirq号中找到
61 如果驱动程序有Linux的IRQ号或irq_data指针，并且需要知道相关的hwirq号（比
62 如在irq_chip回调中），那么可以直接从irq_data->hwirq中获得。
67 从hwirq到Linux irq的反向映射有几种机制，每种机制使用不同的分配函数。应该
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/Linux-v5.15/arch/powerpc/sysdev/
Dmpic_u3msi.c61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_ht_magic_addr() argument
75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq) in find_u4_magic_addr() argument
97 return 0xf8004000 | (hwirq << 4); in find_u4_magic_addr()
105 irq_hw_number_t hwirq; in u3msi_teardown_msi_irqs() local
111 hwirq = virq_to_hw(entry->irq); in u3msi_teardown_msi_irqs()
114 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); in u3msi_teardown_msi_irqs()
126 int hwirq; in u3msi_setup_msi_irqs() local
140 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); in u3msi_setup_msi_irqs()
141 if (hwirq < 0) { in u3msi_setup_msi_irqs()
143 return hwirq; in u3msi_setup_msi_irqs()
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/Linux-v5.15/arch/powerpc/platforms/85xx/
Dsocrates_fpga_pic.c109 unsigned int irq_line, hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_ack() local
112 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_ack()
116 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_ack()
124 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask() local
128 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask()
132 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask()
140 unsigned int hwirq = irqd_to_hwirq(d); in socrates_fpga_pic_mask_ack() local
144 irq_line = fpga_irqs[hwirq].irq_line; in socrates_fpga_pic_mask_ack()
148 mask &= ~(1 << hwirq); in socrates_fpga_pic_mask_ack()
149 mask |= (1 << (hwirq + 16)); in socrates_fpga_pic_mask_ack()
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/Linux-v5.15/drivers/irqchip/
Dirq-pruss-intc.c178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_map() argument
186 intc->event_channel[hwirq].ref_count++; in pruss_intc_map()
188 ch = intc->event_channel[hwirq].value; in pruss_intc_map()
191 pruss_intc_update_cmr(intc, hwirq, ch); in pruss_intc_map()
193 reg_idx = hwirq / 32; in pruss_intc_map()
194 val = BIT(hwirq % 32); in pruss_intc_map()
208 hwirq, ch, host); in pruss_intc_map()
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) in pruss_intc_unmap() argument
229 ch = intc->event_channel[hwirq].value; in pruss_intc_unmap()
240 intc->event_channel[hwirq].ref_count--; in pruss_intc_unmap()
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Dirq-or1k-pic.c28 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask()
33 mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq)); in or1k_pic_unmask()
38 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_ack()
43 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_mask_ack()
44 mtspr(SPR_PICSR, (1UL << data->hwirq)); in or1k_pic_mask_ack()
55 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_ack()
60 mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
61 mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq)); in or1k_pic_or1200_mask_ack()
103 int hwirq; in pic_get_irq() local
105 hwirq = ffs(mfspr(SPR_PICSR) >> first); in pic_get_irq()
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Dirq-ls-extirq.c30 irq_hw_number_t hwirq = data->hwirq; in ls_extirq_set_type() local
34 mask = 1U << (31 - hwirq); in ls_extirq_set_type()
36 mask = 1U << hwirq; in ls_extirq_set_type()
76 irq_hw_number_t hwirq; in ls_extirq_domain_alloc() local
81 hwirq = fwspec->param[0]; in ls_extirq_domain_alloc()
82 if (hwirq >= priv->nirq) in ls_extirq_domain_alloc()
85 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip, in ls_extirq_domain_alloc()
88 return irq_domain_alloc_irqs_parent(domain, virq, 1, &priv->map[hwirq]); in ls_extirq_domain_alloc()
113 u32 hwirq, intsize, j; in ls_extirq_parse_map() local
117 hwirq = be32_to_cpup(map); in ls_extirq_parse_map()
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Dirq-loongson-pch-pic.c71 pch_pic_bitset(priv, PCH_PIC_MASK, d->hwirq); in pch_pic_mask_irq()
79 writel(BIT(PIC_REG_BIT(d->hwirq)), in pch_pic_unmask_irq()
80 priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4); in pch_pic_unmask_irq()
83 pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq); in pch_pic_unmask_irq()
93 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
94 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
98 pch_pic_bitset(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
99 pch_pic_bitset(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
103 pch_pic_bitclr(priv, PCH_PIC_EDGE, d->hwirq); in pch_pic_set_type()
104 pch_pic_bitclr(priv, PCH_PIC_POL, d->hwirq); in pch_pic_set_type()
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Dirq-ativic32.c17 __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2); in ativic32_ack_irq()
23 __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2); in ativic32_mask_irq()
29 __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2); in ativic32_unmask_irq()
36 u32 bit = 1 << data->hwirq; in nointc_set_wake()
40 __assign_bit(data->hwirq, &irq_orig_bit, true); in nointc_set_wake()
42 __assign_bit(data->hwirq, &irq_orig_bit, false); in nointc_set_wake()
44 __assign_bit(data->hwirq, &int_mask, true); in nointc_set_wake()
45 __assign_bit(data->hwirq, &wake_mask, true); in nointc_set_wake()
49 __assign_bit(data->hwirq, &int_mask, false); in nointc_set_wake()
51 __assign_bit(data->hwirq, &wake_mask, false); in nointc_set_wake()
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Dirq-mvebu-sei.c59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
74 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
88 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
144 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
199 unsigned long *hwirq, in mvebu_sei_ap_translate() argument
202 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
213 unsigned long hwirq; in mvebu_sei_ap_alloc() local
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Dirq-ixp4xx.c78 if (ixi->is_356 && d->hwirq >= 32) { in ixp4xx_irq_mask()
80 val &= ~BIT(d->hwirq - 32); in ixp4xx_irq_mask()
84 val &= ~BIT(d->hwirq); in ixp4xx_irq_mask()
98 if (ixi->is_356 && d->hwirq >= 32) { in ixp4xx_irq_unmask()
100 val |= BIT(d->hwirq - 32); in ixp4xx_irq_unmask()
104 val |= BIT(d->hwirq); in ixp4xx_irq_unmask()
131 unsigned long *hwirq, in ixp4xx_irq_domain_translate() argument
136 *hwirq = fwspec->param[0]; in ixp4xx_irq_domain_translate()
144 *hwirq = fwspec->param[0]; in ixp4xx_irq_domain_translate()
158 irq_hw_number_t hwirq; in ixp4xx_irq_domain_alloc() local
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Dirq-mbigen.c67 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) in get_mbigen_vec_reg() argument
71 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_vec_reg()
72 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_vec_reg()
73 pin = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_vec_reg()
79 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, in get_mbigen_type_reg() argument
84 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; in get_mbigen_type_reg()
85 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; in get_mbigen_type_reg()
86 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; in get_mbigen_type_reg()
95 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, in get_mbigen_clear_reg() argument
98 unsigned int ofst = (hwirq / 32) * 4; in get_mbigen_clear_reg()
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Dirq-xilinx-intc.c65 unsigned long mask = BIT(d->hwirq); in intc_enable_or_unmask()
67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
83 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
84 xintc_write(irqc, CIE, BIT(d->hwirq)); in intc_disable_or_mask()
91 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
92 xintc_write(irqc, IAR, BIT(d->hwirq)); in intc_ack()
98 unsigned long mask = BIT(d->hwirq); in intc_mask_ack()
100 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
116 u32 hwirq; in xintc_get_irq() local
118 hwirq = xintc_read(primary_intc, IVR); in xintc_get_irq()
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Dirq-partition-percpu.c26 unsigned int cpu, unsigned int hwirq) in partition_check_cpu() argument
28 return cpumask_test_cpu(cpu, &part->parts[hwirq].mask); in partition_check_cpu()
37 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_mask()
48 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_unmask()
61 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_set_irqchip_state()
76 if (partition_check_cpu(part, smp_processor_id(), d->hwirq) && in partition_irq_get_irqchip_state()
101 seq_printf(p, " %5s-%lu", chip->name, data->hwirq); in partition_irq_print_chip()
118 int hwirq; in partition_handle_irq() local
122 for_each_set_bit(hwirq, part->bitmap, part->nr_parts) { in partition_handle_irq()
123 if (partition_check_cpu(part, cpu, hwirq)) in partition_handle_irq()
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Dirq-sifive-plic.c85 int hwirq, int enable) in plic_toggle() argument
87 u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); in plic_toggle()
88 u32 hwirq_mask = 1 << (hwirq % 32); in plic_toggle()
104 writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
110 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
166 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); in plic_irq_eoi()
180 irq_hw_number_t hwirq) in plic_irqdomain_map() argument
184 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, in plic_irqdomain_map()
195 irq_hw_number_t hwirq; in plic_irq_domain_alloc() local
199 ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); in plic_irq_domain_alloc()
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Dirq-sni-exiu.c44 writel(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_eoi()
53 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq); in exiu_irq_mask()
63 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_unmask()
74 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_enable()
76 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq); in exiu_irq_enable()
88 val |= BIT(d->hwirq); in exiu_irq_set_type()
90 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
95 val &= ~BIT(d->hwirq); in exiu_irq_set_type()
97 val |= BIT(d->hwirq); in exiu_irq_set_type()
100 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); in exiu_irq_set_type()
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Dirq-mmp.c71 int hwirq; in icu_mask_ack_irq() local
74 hwirq = d->irq - data->virq_base; in icu_mask_ack_irq()
76 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
79 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 && (hwirq == data->clr_mfp_hwirq)) in icu_mask_ack_irq()
86 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
95 int hwirq; in icu_mask_irq() local
98 hwirq = d->irq - data->virq_base; in icu_mask_irq()
100 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
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/Linux-v5.15/arch/powerpc/platforms/powernv/
Dpci-cxl.c42 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); in pnv_cxl_alloc_hwirqs() local
44 if (hwirq < 0) { in pnv_cxl_alloc_hwirqs()
49 return phb->msi_base + hwirq; in pnv_cxl_alloc_hwirqs()
53 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) in pnv_cxl_release_hwirqs() argument
58 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); in pnv_cxl_release_hwirqs()
67 int i, hwirq; in pnv_cxl_release_hwirq_ranges() local
75 hwirq = irqs->offset[i] - phb->msi_base; in pnv_cxl_release_hwirq_ranges()
76 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, in pnv_cxl_release_hwirq_ranges()
87 int i, hwirq, try; in pnv_cxl_alloc_hwirq_ranges() local
95 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); in pnv_cxl_alloc_hwirq_ranges()
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/Linux-v5.15/arch/powerpc/platforms/pasemi/
Dmsi.c61 irq_hw_number_t hwirq; in pasemi_msi_teardown_msi_irqs() local
69 hwirq = virq_to_hw(entry->irq); in pasemi_msi_teardown_msi_irqs()
72 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK); in pasemi_msi_teardown_msi_irqs()
83 int hwirq; in pasemi_msi_setup_msi_irqs() local
99 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, in pasemi_msi_setup_msi_irqs()
101 if (hwirq < 0) { in pasemi_msi_setup_msi_irqs()
103 return hwirq; in pasemi_msi_setup_msi_irqs()
106 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); in pasemi_msi_setup_msi_irqs()
109 hwirq); in pasemi_msi_setup_msi_irqs()
110 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, in pasemi_msi_setup_msi_irqs()
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/Linux-v5.15/drivers/pinctrl/mediatek/
Dmtk-eint.c85 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) in mtk_eint_flip_edge() argument
89 u32 mask = BIT(hwirq & 0x1f); in mtk_eint_flip_edge()
90 u32 port = (hwirq >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
93 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
104 hwirq); in mtk_eint_flip_edge()
113 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_mask()
114 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
117 eint->cur_mask[d->hwirq >> 5] &= ~mask; in mtk_eint_mask()
125 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_unmask()
126 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_unmask()
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/Linux-v5.15/arch/arm/mach-imx/
Dgpc.c91 unsigned int idx = d->hwirq / 32; in imx_gpc_irq_set_wake()
94 mask = 1 << d->hwirq % 32; in imx_gpc_irq_set_wake()
125 void imx_gpc_hwirq_unmask(unsigned int hwirq) in imx_gpc_hwirq_unmask() argument
130 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_unmask()
132 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
136 void imx_gpc_hwirq_mask(unsigned int hwirq) in imx_gpc_hwirq_mask() argument
141 reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; in imx_gpc_hwirq_mask()
143 val |= 1 << (hwirq % 32); in imx_gpc_hwirq_mask()
149 imx_gpc_hwirq_unmask(d->hwirq); in imx_gpc_irq_unmask()
155 imx_gpc_hwirq_mask(d->hwirq); in imx_gpc_irq_mask()
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/Linux-v5.15/drivers/pci/controller/
Dpcie-iproc-msi.c146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
148 return (hwirq % msi->nr_irqs); in hwirq_to_group()
152 unsigned long hwirq) in iproc_msi_addr_offset() argument
155 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
157 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
197 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
201 unsigned long hwirq) in hwirq_to_canonical_hwirq()
203 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
214 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
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/Linux-v5.15/drivers/gpio/
Dgpio-hlwd.c65 int hwirq; in hlwd_gpio_irqhandler() local
100 for_each_set_bit(hwirq, &pending, 32) in hlwd_gpio_irqhandler()
101 generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq); in hlwd_gpio_irqhandler()
111 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG); in hlwd_gpio_irq_ack()
123 mask &= ~BIT(data->hwirq); in hlwd_gpio_irq_mask()
137 mask |= BIT(data->hwirq); in hlwd_gpio_irq_unmask()
148 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq, in hlwd_gpio_irq_setup_emulation() argument
155 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
156 level &= ~BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
157 level |= state ^ BIT(hwirq); in hlwd_gpio_irq_setup_emulation()
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/Linux-v5.15/drivers/misc/cxl/
Dirq.c173 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); in cxl_irq_afu() local
191 irq_off = hwirq - ctx->irqs.offset[r]; in cxl_irq_afu()
201 ctx->pe, irq, hwirq); in cxl_irq_afu()
205 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); in cxl_irq_afu()
207 afu_irq, ctx->pe, irq, hwirq); in cxl_irq_afu()
223 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, in cxl_map_irq() argument
230 virq = irq_create_mapping(NULL, hwirq); in cxl_map_irq()
237 cxl_ops->setup_irq(adapter, hwirq, virq); in cxl_map_irq()
239 pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq); in cxl_map_irq()
262 int hwirq, virq; in cxl_register_one_irq() local
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/Linux-v5.15/kernel/irq/
Dirqdomain.c503 irq_hw_number_t hwirq) in irq_domain_clear_mapping() argument
509 if (hwirq < domain->revmap_size) in irq_domain_clear_mapping()
510 rcu_assign_pointer(domain->revmap[hwirq], NULL); in irq_domain_clear_mapping()
512 radix_tree_delete(&domain->revmap_tree, hwirq); in irq_domain_clear_mapping()
517 irq_hw_number_t hwirq, in irq_domain_set_mapping() argument
524 if (hwirq < domain->revmap_size) in irq_domain_set_mapping()
525 rcu_assign_pointer(domain->revmap[hwirq], irq_data); in irq_domain_set_mapping()
527 radix_tree_insert(&domain->revmap_tree, hwirq, irq_data); in irq_domain_set_mapping()
534 irq_hw_number_t hwirq; in irq_domain_disassociate() local
540 hwirq = irq_data->hwirq; in irq_domain_disassociate()
[all …]
/Linux-v5.15/arch/powerpc/sysdev/ge/
Dge_pic.c114 unsigned int hwirq = irqd_to_hwirq(d); in gef_pic_mask() local
119 mask &= ~(1 << hwirq); in gef_pic_mask()
135 unsigned int hwirq = irqd_to_hwirq(d); in gef_pic_unmask() local
140 mask |= (1 << hwirq); in gef_pic_unmask()
157 irq_hw_number_t hwirq) in gef_pic_host_map() argument
232 int hwirq; in gef_pic_get_irq() local
241 for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) { in gef_pic_get_irq()
242 if (active & (0x1 << hwirq)) in gef_pic_get_irq()
246 (irq_hw_number_t)hwirq); in gef_pic_get_irq()

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