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Searched refs:gfx (Results 1 – 25 of 112) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c45 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
46 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
47 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
56 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
57 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
59 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
60 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
68 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
76 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
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Dgfx_v6_0.c341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
[all …]
Dgfx_v7_0.c930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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Dgfx_v9_0.c951 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1019 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
1020 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
1021 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
1154 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1155 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1156 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1157 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1158 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1159 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
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Dgfx_v8_0.c840 adev->gfx.scratch.num_reg = 8; in gfx_v8_0_scratch_init()
841 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
842 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v8_0_scratch_init()
941 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
942 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
943 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
944 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
945 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
946 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
947 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
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Dgfx_v10_0.c3725 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3827 adev->gfx.scratch.num_reg = 8; in gfx_v10_0_scratch_init()
3828 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
3829 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v10_0_scratch_init()
3968 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3969 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3970 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3971 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3972 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3973 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
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Damdgpu_atomfirmware.c643 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
644 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
645 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
646 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
647 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
648 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
649 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
650 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
651 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
653 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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Damdgpu_discovery.c432 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); in amdgpu_discovery_get_gfx_info()
433 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
435 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
436 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
437 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
438 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); in amdgpu_discovery_get_gfx_info()
439 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
440 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
441 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
442 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
[all …]
Damdgpu_kms.c299 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
300 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
303 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
304 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
307 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
308 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
311 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
312 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
315 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
316 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
[all …]
Damdgpu_amdkfd.c123 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
124 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
137 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
144 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
145 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
371 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
374 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
377 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
380 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
383 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
Damdgpu_amdkfd_gfx_v9.c76 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
77 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
85 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
180 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
181 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
321 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
330 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
331 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
336 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
363 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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Damdgpu_debugfs.c205 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
206 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
671 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
672 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
673 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
674 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
675 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
676 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
677 config[no_regs++] = adev->gfx.config.max_gprs; in amdgpu_debugfs_gca_config_read()
678 config[no_regs++] = adev->gfx.config.max_gs_threads; in amdgpu_debugfs_gca_config_read()
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Damdgpu_ucode.c518 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
519 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
520 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
521 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
522 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
523 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
524 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
525 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
526 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
648 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
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Dsoc15_common.h31 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \
32 adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
36 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \
37 adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
Damdgpu_amdkfd_gfx_v10_3.c68 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
69 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
77 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
127 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
128 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
210 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
211 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
303 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
304 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
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Damdgpu_amdkfd_gfx_v10.c69 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
70 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
78 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
159 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
160 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
309 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
318 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hiq_mqd_load()
319 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hiq_mqd_load()
324 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
351 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
Dgfx_v9_4_2.c433 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) { in gfx_v9_4_2_log_wave_assignment()
465 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) in gfx_v9_4_2_wait_for_waves_assigned()
493 int wb_size = adev->gfx.config.max_shader_engines * in gfx_v9_4_2_do_sgprs_init()
501 if (!adev->gfx.compute_ring[0].sched.ready || in gfx_v9_4_2_do_sgprs_init()
502 !adev->gfx.compute_ring[1].sched.ready) in gfx_v9_4_2_do_sgprs_init()
516 &adev->gfx.compute_ring[0], in gfx_v9_4_2_do_sgprs_init()
522 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
532 adev->gfx.cu_info.number * SIMD_ID_MAX * 2, in gfx_v9_4_2_do_sgprs_init()
541 &adev->gfx.compute_ring[1], in gfx_v9_4_2_do_sgprs_init()
547 adev->gfx.cu_info.number * 2, in gfx_v9_4_2_do_sgprs_init()
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Dvcn_v1_0.c336 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
338 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
340 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
342 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
344 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
346 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
348 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
350 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
352 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
354 adev->gfx.config.gb_addr_config); in vcn_v1_0_mc_resume_spg_mode()
[all …]
Damdgpu_virt.c68 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
525 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
526 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
527 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
528 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
529 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
530 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
531 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
532 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
Damdgpu_ras.c843 if (adev->gfx.ras_funcs && in amdgpu_ras_query_error_status()
844 adev->gfx.ras_funcs->query_ras_error_count) in amdgpu_ras_query_error_status()
845 adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data); in amdgpu_ras_query_error_status()
847 if (adev->gfx.ras_funcs && in amdgpu_ras_query_error_status()
848 adev->gfx.ras_funcs->query_ras_error_status) in amdgpu_ras_query_error_status()
849 adev->gfx.ras_funcs->query_ras_error_status(adev); in amdgpu_ras_query_error_status()
935 if (adev->gfx.ras_funcs && in amdgpu_ras_reset_error_status()
936 adev->gfx.ras_funcs->reset_ras_error_count) in amdgpu_ras_reset_error_status()
937 adev->gfx.ras_funcs->reset_ras_error_count(adev); in amdgpu_ras_reset_error_status()
939 if (adev->gfx.ras_funcs && in amdgpu_ras_reset_error_status()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt8 - compatible: "aspeed,ast2500-gfx", "syscon"
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v5.15/arch/arm/boot/dts/
Daspeed-bmc-intel-s2600wf.dts117 &gfx {
122 aspeed,external-nodes = <&gfx &lhc>;

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