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Searched refs:emc (Results 1 – 25 of 54) sorted by relevance

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/Linux-v5.15/drivers/memory/tegra/
Dtegra20-emc.c208 struct tegra_emc *emc = data; in tegra_emc_isr() local
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
218 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
227 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
233 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
234 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
235 timing = &emc->timings[i]; in tegra_emc_find_timing()
241 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
248 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
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Dtegra210-emc-core.c561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
578 static void tegra210_emc_training_start(struct tegra210_emc *emc) in tegra210_emc_training_start() argument
580 mod_timer(&emc->training, in tegra210_emc_training_start()
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Dtegra30-emc.c383 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
388 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
390 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
394 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
403 struct tegra_emc *emc = data; in tegra_emc_isr() local
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
413 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
422 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, in emc_find_timing() argument
428 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
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Dtegra186-emc.c59 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument
64 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
65 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
74 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show() local
78 for (i = 0; i < emc->num_dvfs; i++) { in tegra186_emc_debug_available_rates_show()
79 seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate); in tegra186_emc_debug_available_rates_show()
104 struct tegra186_emc *emc = data; in tegra186_emc_debug_min_rate_get() local
106 *rate = emc->debugfs.min_rate; in tegra186_emc_debug_min_rate_get()
113 struct tegra186_emc *emc = data; in tegra186_emc_debug_min_rate_set() local
116 if (!tegra186_emc_validate_rate(emc, rate)) in tegra186_emc_debug_min_rate_set()
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Dtegra124-emc.c518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
550 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
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Dtegra210-emc-cc-r21021.c36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
116 static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) in update_clock_tree_delay() argument
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay()
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay()
134 value = tegra210_emc_mrr_read(emc, 2, 19); in update_clock_tree_delay()
136 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
145 value = tegra210_emc_mrr_read(emc, 2, 18); in update_clock_tree_delay()
147 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
206 if (emc->num_channels > 1) { in update_clock_tree_delay()
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Dtegra210-emc-table.c15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
35 if (emc->derated) { in tegra210_emc_table_device_init()
40 if (emc->nominal) { in tegra210_emc_table_device_init()
41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
43 count, emc->num_timings); in tegra210_emc_table_device_init()
48 emc->derated = timings; in tegra210_emc_table_device_init()
50 emc->num_timings = count; in tegra210_emc_table_device_init()
51 emc->nominal = timings; in tegra210_emc_table_device_init()
65 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_release() local
67 if ((emc->nominal && timings != emc->nominal) && in tegra210_emc_table_device_release()
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DMakefile15 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
16 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
17 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
18 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
19 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
20 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
21 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
23 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
Dtegra210-emc.h939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
940 u32 (*periodic_compensation)(struct tegra210_emc *emc);
943 static inline void emc_writel(struct tegra210_emc *emc, u32 value, in emc_writel() argument
946 writel_relaxed(value, emc->regs + offset); in emc_writel()
949 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) in emc_readl() argument
951 return readl_relaxed(emc->regs + offset); in emc_readl()
954 static inline void emc_channel_writel(struct tegra210_emc *emc, in emc_channel_writel() argument
958 writel_relaxed(value, emc->channel[channel] + offset); in emc_channel_writel()
961 static inline u32 emc_channel_readl(struct tegra210_emc *emc, in emc_channel_readl() argument
964 return readl_relaxed(emc->channel[channel] + offset); in emc_channel_readl()
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/Linux-v5.15/arch/arm/boot/dts/
Dtegra124-jetson-tk1-emc.dtsi4 emc-timings-3 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
59 clock-names = "emc-parent";
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Dtegra124-apalis-emc.dtsi9 emc-timings-1 {
16 clock-names = "emc-parent";
22 clock-names = "emc-parent";
28 clock-names = "emc-parent";
34 clock-names = "emc-parent";
40 clock-names = "emc-parent";
46 clock-names = "emc-parent";
52 clock-names = "emc-parent";
58 clock-names = "emc-parent";
64 clock-names = "emc-parent";
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Dtegra124-nyan-blaze-emc.dtsi4 emc-timings-1 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
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Dtegra124-nyan-big-emc.dtsi8 emc-timings-1 {
15 clock-names = "emc-parent";
21 clock-names = "emc-parent";
27 clock-names = "emc-parent";
33 clock-names = "emc-parent";
39 clock-names = "emc-parent";
45 clock-names = "emc-parent";
51 clock-names = "emc-parent";
57 clock-names = "emc-parent";
63 clock-names = "emc-parent";
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Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
159 emc-timings-1 {
315 emc-timings-0 {
321 nvidia,emc-auto-cal-interval = <0x001fffff>;
322 nvidia,emc-mode-1 = <0x80100003>;
323 nvidia,emc-mode-2 = <0x80200008>;
324 nvidia,emc-mode-reset = <0x80001221>;
325 nvidia,emc-zcal-cnt-long = <0x00000040>;
326 nvidia,emc-cfg-dyn-self-ref;
327 nvidia,emc-cfg-periodic-qrst;
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Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
22 nvidia,emc-cfg-periodic-qrst;
24 nvidia,emc-configuration = <
118 emc-timings-1 {
122 nvidia,emc-auto-cal-interval = <0x001fffff>;
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Dtegra20-acer-a500-picasso.dts1111 emc-tables@0 {
1118 emc-table@25000 {
1120 compatible = "nvidia,tegra20-emc-table";
1122 nvidia,emc-registers = <0x00000002 0x00000006
1136 emc-table@50000 {
1138 compatible = "nvidia,tegra20-emc-table";
1140 nvidia,emc-registers = <0x00000003 0x00000007
1154 emc-table@75000 {
1156 compatible = "nvidia,tegra20-emc-table";
1158 nvidia,emc-registers = <0x00000005 0x0000000a
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Dtegra30-ouya.dts593 emc-timings-0 {
734 emc-timings-1 {
875 emc-timings-2 {
1018 emc-timings-0 {
1022 nvidia,emc-auto-cal-interval = <0x001fffff>;
1023 nvidia,emc-mode-1 = <0x80100003>;
1024 nvidia,emc-mode-2 = <0x80200008>;
1025 nvidia,emc-mode-reset = <0x80001221>;
1026 nvidia,emc-zcal-cnt-long = <0x00000040>;
1027 nvidia,emc-cfg-periodic-qrst;
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Dlpc4350-hitex-eval.dts139 emc_pins: emc-pins {
147 function = "emc";
159 function = "emc";
168 function = "emc";
177 function = "emc";
186 function = "emc";
195 function = "emc";
204 function = "emc";
213 function = "emc";
222 function = "emc";
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Dlpc4357-ea4357-devkit.dts165 emc_pins: emc-pins {
173 function = "emc";
189 function = "emc";
198 function = "emc";
207 function = "emc";
216 function = "emc";
225 function = "emc";
234 function = "emc";
243 function = "emc";
252 function = "emc";
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Dlpc4357-myd-lpc4357.dts116 emc_pins: emc-pins {
124 function = "emc";
134 function = "emc";
143 function = "emc";
150 function = "emc";
157 function = "emc";
164 function = "emc";
171 function = "emc";
178 function = "emc";
185 function = "emc";
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/Linux-v5.15/drivers/clk/tegra/
Dclk-tegra20-emc.c57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
78 val = readl_relaxed(emc->reg); in emc_set_parent()
84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
89 if (emc->mc_same_freq) in emc_set_parent()
94 writel_relaxed(val, emc->reg); in emc_set_parent()
96 fence_udelay(1, emc->reg); in emc_set_parent()
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Dclk-tegra210-emc.c53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_round_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_round_rate()
107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
110 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
121 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_set_rate() local
122 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_set_rate()
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DMakefile19 obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20-emc.o
21 obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o
25 obj-$(CONFIG_TEGRA124_CLK_EMC) += clk-tegra124-emc.o
29 obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210-emc.o
Dclk-tegra124-emc.c79 struct tegra_emc *emc; member
180 if (tegra->emc) in emc_ensure_emc_driver()
181 return tegra->emc; in emc_ensure_emc_driver()
199 tegra->emc = platform_get_drvdata(pdev); in emc_ensure_emc_driver()
200 if (!tegra->emc) { in emc_ensure_emc_driver()
205 return tegra->emc; in emc_ensure_emc_driver()
215 struct tegra_emc *emc = emc_ensure_emc_driver(tegra); in emc_set_timing() local
217 if (!emc) in emc_set_timing()
251 err = tegra->prepare_timing_change(emc, timing->rate); in emc_set_timing()
271 tegra->complete_timing_change(emc, timing->rate); in emc_set_timing()
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi62 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
63 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
434 emc: external-memory-controller@2c60000 { label
435 compatible = "nvidia,tegra194-emc";
439 clock-names = "emc";
734 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
735 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
761 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
762 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
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