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Searched refs:dev_priv (Results 1 – 25 of 275) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_pch.c11 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) in intel_pch_type() argument
15 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
16 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
19 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
20 drm_WARN_ON(&dev_priv->drm, in intel_pch_type()
21 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
24 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
25 drm_WARN_ON(&dev_priv->drm, in intel_pch_type()
26 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
30 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
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Di915_irq.c182 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) in intel_hpd_init_pins() argument
184 struct i915_hotplug *hpd = &dev_priv->hotplug; in intel_hpd_init_pins()
186 if (HAS_GMCH(dev_priv)) { in intel_hpd_init_pins()
187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
188 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
195 if (DISPLAY_VER(dev_priv) >= 11) in intel_hpd_init_pins()
197 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
199 else if (DISPLAY_VER(dev_priv) >= 8) in intel_hpd_init_pins()
201 else if (DISPLAY_VER(dev_priv) >= 7) in intel_hpd_init_pins()
206 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && in intel_hpd_init_pins()
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Di915_drv.c92 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) in i915_get_bridge_dev() argument
94 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); in i915_get_bridge_dev()
96 dev_priv->bridge_dev = in i915_get_bridge_dev()
98 if (!dev_priv->bridge_dev) { in i915_get_bridge_dev()
99 drm_err(&dev_priv->drm, "bridge device not found\n"); in i915_get_bridge_dev()
107 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) in intel_alloc_mchbar_resource() argument
109 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
114 if (GRAPHICS_VER(dev_priv) >= 4) in intel_alloc_mchbar_resource()
115 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); in intel_alloc_mchbar_resource()
116 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); in intel_alloc_mchbar_resource()
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Di915_suspend.c36 static void intel_save_swf(struct drm_i915_private *dev_priv) in intel_save_swf() argument
41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
48 } else if (GRAPHICS_VER(dev_priv) == 2) { in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
51 } else if (HAS_GMCH(dev_priv)) { in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
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Di915_drv.h198 struct drm_i915_private *dev_priv; member
327 void (*get_cdclk)(struct drm_i915_private *dev_priv,
329 void (*set_cdclk)(struct drm_i915_private *dev_priv,
333 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
371 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
372 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
538 struct drm_i915_private *dev_priv; member
1300 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1301 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) argument
1302 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
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Dintel_pch.h64 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
65 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
66 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
67 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
68 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
69 #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) argument
70 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) argument
71 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
72 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
73 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
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Dintel_gvt.c44 static bool is_supported_device(struct drm_i915_private *dev_priv) in is_supported_device() argument
46 if (IS_BROADWELL(dev_priv)) in is_supported_device()
48 if (IS_SKYLAKE(dev_priv)) in is_supported_device()
50 if (IS_KABYLAKE(dev_priv)) in is_supported_device()
52 if (IS_BROXTON(dev_priv)) in is_supported_device()
54 if (IS_COFFEELAKE(dev_priv)) in is_supported_device()
56 if (IS_COMETLAKE(dev_priv)) in is_supported_device()
68 void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) in intel_gvt_sanitize_options() argument
70 if (!dev_priv->params.enable_gvt) in intel_gvt_sanitize_options()
73 if (intel_vgpu_active(dev_priv)) { in intel_gvt_sanitize_options()
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/Linux-v5.15/drivers/gpu/drm/via/
Dvia_dma.c66 dev_priv->dma_low += 8; \
74 dev_priv->dma_low += 8; \
77 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
78 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
79 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
80 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
81 static int via_wait_idle(drm_via_private_t *dev_priv);
82 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
88 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) in via_cmdbuf_space() argument
90 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; in via_cmdbuf_space()
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Dvia_irq.c95 drm_via_private_t *dev_priv = dev->dev_private; in via_get_vblank_counter() local
100 return atomic_read(&dev_priv->vbl_received); in via_get_vblank_counter()
106 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; in via_driver_irq_handler() local
110 drm_via_irq_t *cur_irq = dev_priv->via_irqs; in via_driver_irq_handler()
113 status = via_read(dev_priv, VIA_REG_INTERRUPT); in via_driver_irq_handler()
115 atomic_inc(&dev_priv->vbl_received); in via_driver_irq_handler()
116 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { in via_driver_irq_handler()
118 if (dev_priv->last_vblank_valid) { in via_driver_irq_handler()
119 dev_priv->nsec_per_vblank = in via_driver_irq_handler()
121 dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
[all …]
/Linux-v5.15/drivers/gpu/drm/savage/
Dsavage_bci.c47 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
49 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
50 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
55 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
62 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
76 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
78 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
97 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
99 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
129 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
/Linux-v5.15/drivers/gpu/drm/vmwgfx/
Dvmwgfx_drv.c363 static void vmw_print_sm_type(struct vmw_private *dev_priv) in vmw_print_sm_type() argument
373 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
374 names[dev_priv->sm_type]); in vmw_print_sm_type()
390 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
407 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, in vmw_dummy_query_bo_create()
432 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
437 static int vmw_device_init(struct vmw_private *dev_priv) in vmw_device_init() argument
441 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
442 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_device_init()
443 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
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Dvmwgfx_irq.c49 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
53 dev_priv->irqthread_pending)) { in vmw_thread_fn()
54 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
55 wake_up_all(&dev_priv->fence_queue); in vmw_thread_fn()
60 dev_priv->irqthread_pending)) { in vmw_thread_fn()
61 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
82 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_irq_handler() local
86 status = vmw_irq_status_read(dev_priv); in vmw_irq_handler()
87 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
90 vmw_irq_status_write(dev_priv, status); in vmw_irq_handler()
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Dvmwgfx_cmd.c35 bool vmw_supports_3d(struct vmw_private *dev_priv) in vmw_supports_3d() argument
38 const struct vmw_fifo_state *fifo = dev_priv->fifo; in vmw_supports_3d()
40 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_supports_3d()
43 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_supports_3d()
46 if (!dev_priv->has_mob) in vmw_supports_3d()
49 result = vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_3D); in vmw_supports_3d()
54 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) in vmw_supports_3d()
57 BUG_ON(vmw_is_svga_v3(dev_priv)); in vmw_supports_3d()
59 fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN); in vmw_supports_3d()
63 hwversion = vmw_fifo_mem_read(dev_priv, in vmw_supports_3d()
[all …]
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_cdclk.c62 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
68 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
74 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
80 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
86 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
92 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
98 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
101 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
140 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
143 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
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Dintel_fbc.c65 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, in intel_fbc_calculate_cfb_size() argument
71 if (DISPLAY_VER(dev_priv) == 7) in intel_fbc_calculate_cfb_size()
73 else if (DISPLAY_VER(dev_priv) >= 8) in intel_fbc_calculate_cfb_size()
80 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) in i8xx_fbc_deactivate() argument
85 fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); in i8xx_fbc_deactivate()
90 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
93 if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, in i8xx_fbc_deactivate()
95 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n"); in i8xx_fbc_deactivate()
100 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) in i8xx_fbc_activate() argument
102 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in i8xx_fbc_activate()
[all …]
Dintel_fifo_underrun.c57 struct drm_i915_private *dev_priv = to_i915(dev); in ivb_can_enable_err_int() local
61 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
63 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
64 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
75 struct drm_i915_private *dev_priv = to_i915(dev); in cpt_can_enable_serr_int() local
79 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
81 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
82 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
93 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns() local
97 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
[all …]
Dintel_fdi.c23 struct drm_i915_private *dev_priv = to_i915(dev); in ilk_check_fdi_lanes() local
28 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
32 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
38 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
40 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
49 if (INTEL_NUM_PIPES(dev_priv) == 2) in ilk_check_fdi_lanes()
60 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); in ilk_check_fdi_lanes()
67 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
75 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
81 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
[all …]
Dintel_gmbus.c102 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, in get_gmbus_pin() argument
105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in get_gmbus_pin()
107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in get_gmbus_pin()
109 else if (HAS_PCH_CNP(dev_priv)) in get_gmbus_pin()
111 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_gmbus_pin()
113 else if (DISPLAY_VER(dev_priv) == 9) in get_gmbus_pin()
115 else if (IS_BROADWELL(dev_priv)) in get_gmbus_pin()
121 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, in intel_gmbus_is_valid_pin() argument
126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in intel_gmbus_is_valid_pin()
128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in intel_gmbus_is_valid_pin()
[all …]
Dintel_hotplug.c86 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, in intel_hpd_pin_default() argument
139 static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, in intel_hpd_irq_storm_detect() argument
142 struct i915_hotplug *hpd = &dev_priv->hotplug; in intel_hpd_irq_storm_detect()
150 (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
161 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
165 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
175 intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) in intel_hpd_irq_storm_switch_to_polling() argument
177 struct drm_device *dev = &dev_priv->drm; in intel_hpd_irq_storm_switch_to_polling()
182 lockdep_assert_held(&dev_priv->irq_lock); in intel_hpd_irq_storm_switch_to_polling()
193 dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED) in intel_hpd_irq_storm_switch_to_polling()
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Dintel_combo_phy.c42 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
47 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
72 static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, in icl_set_procmon_ref_values() argument
78 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
80 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in icl_set_procmon_ref_values()
83 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in icl_set_procmon_ref_values()
85 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
86 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
89 static bool check_phy_reg(struct drm_i915_private *dev_priv, in check_phy_reg() argument
93 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
[all …]
Dintel_lpe_audio.c77 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL) argument
80 lpe_audio_platdev_create(struct drm_i915_private *dev_priv) in lpe_audio_platdev_create() argument
82 struct drm_device *dev = &dev_priv->drm; in lpe_audio_platdev_create()
99 rsc[0].start = rsc[0].end = dev_priv->lpe_audio.irq; in lpe_audio_platdev_create()
119 pdata->num_pipes = INTEL_NUM_PIPES(dev_priv); in lpe_audio_platdev_create()
120 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
131 drm_err(&dev_priv->drm, in lpe_audio_platdev_create()
141 static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) in lpe_audio_platdev_destroy() argument
151 platform_device_unregister(dev_priv->lpe_audio.platdev); in lpe_audio_platdev_destroy()
168 static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) in lpe_audio_irq_init() argument
[all …]
Dintel_display_power.c25 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
166 static void intel_power_well_enable(struct drm_i915_private *dev_priv, in intel_power_well_enable() argument
169 drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name); in intel_power_well_enable()
170 power_well->desc->ops->enable(dev_priv, power_well); in intel_power_well_enable()
174 static void intel_power_well_disable(struct drm_i915_private *dev_priv, in intel_power_well_disable() argument
177 drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name); in intel_power_well_disable()
179 power_well->desc->ops->disable(dev_priv, power_well); in intel_power_well_disable()
182 static void intel_power_well_get(struct drm_i915_private *dev_priv, in intel_power_well_get() argument
186 intel_power_well_enable(dev_priv, power_well); in intel_power_well_get()
189 static void intel_power_well_put(struct drm_i915_private *dev_priv, in intel_power_well_put() argument
[all …]
/Linux-v5.15/drivers/gpu/drm/r128/
Dr128_cce.c56 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
63 static void r128_status(drm_r128_private_t *dev_priv) in r128_status() argument
84 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) in r128_do_pixcache_flush() argument
92 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
104 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) in r128_do_wait_for_fifo() argument
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
121 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) in r128_do_wait_for_idle() argument
125 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
129 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
131 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
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/Linux-v5.15/drivers/gpu/drm/mga/
Dmga_dma.c53 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) in mga_do_wait_for_idle() argument
59 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
75 static int mga_do_dma_reset(drm_mga_private_t *dev_priv) in mga_do_dma_reset() argument
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
103 void mga_do_dma_flush(drm_mga_private_t *dev_priv) in mga_do_dma_flush() argument
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
113 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
125 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
148 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); in mga_do_dma_flush()
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/Linux-v5.15/drivers/gpu/drm/gma500/
Dpsb_drv.c101 void psb_spank(struct drm_psb_private *dev_priv) in psb_spank() argument
122 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
127 struct drm_psb_private *dev_priv = dev->dev_private; in psb_do_init() local
128 struct psb_gtt *pg = &dev_priv->gtt; in psb_do_init()
141 dev_priv->gatt_free_offset = pg->mmu_gatt_start + in psb_do_init()
144 spin_lock_init(&dev_priv->irqmask_lock); in psb_do_init()
155 psb_spank(dev_priv); in psb_do_init()
166 struct drm_psb_private *dev_priv = dev->dev_private; in psb_driver_unload() local
170 if (dev_priv) { in psb_driver_unload()
171 if (dev_priv->backlight_device) in psb_driver_unload()
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