62 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_133mhz_get_cdclk()  argument
68 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_200mhz_get_cdclk()  argument
74 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_266mhz_get_cdclk()  argument
80 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_333mhz_get_cdclk()  argument
86 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_400mhz_get_cdclk()  argument
92 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,  in fixed_450mhz_get_cdclk()  argument
98 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,  in i85x_get_cdclk()  argument
101 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in i85x_get_cdclk()
140 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,  in i915gm_get_cdclk()  argument
143 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in i915gm_get_cdclk()
164 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,  in i945gm_get_cdclk()  argument
167 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in i945gm_get_cdclk()
188 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)  in intel_hpll_vco()  argument
232 	if (IS_GM45(dev_priv))  in intel_hpll_vco()
234 	else if (IS_G45(dev_priv))  in intel_hpll_vco()
236 	else if (IS_I965GM(dev_priv))  in intel_hpll_vco()
238 	else if (IS_PINEVIEW(dev_priv))  in intel_hpll_vco()
240 	else if (IS_G33(dev_priv))  in intel_hpll_vco()
245 	tmp = intel_de_read(dev_priv,  in intel_hpll_vco()
246 			    IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);  in intel_hpll_vco()
250 		drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",  in intel_hpll_vco()
253 		drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);  in intel_hpll_vco()
258 static void g33_get_cdclk(struct drm_i915_private *dev_priv,  in g33_get_cdclk()  argument
261 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in g33_get_cdclk()
270 	cdclk_config->vco = intel_hpll_vco(dev_priv);  in g33_get_cdclk()
301 	drm_err(&dev_priv->drm,  in g33_get_cdclk()
307 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,  in pnv_get_cdclk()  argument
310 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in pnv_get_cdclk()
329 		drm_err(&dev_priv->drm,  in pnv_get_cdclk()
341 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,  in i965gm_get_cdclk()  argument
344 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in i965gm_get_cdclk()
352 	cdclk_config->vco = intel_hpll_vco(dev_priv);  in i965gm_get_cdclk()
380 	drm_err(&dev_priv->drm,  in i965gm_get_cdclk()
386 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,  in gm45_get_cdclk()  argument
389 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in gm45_get_cdclk()
393 	cdclk_config->vco = intel_hpll_vco(dev_priv);  in gm45_get_cdclk()
409 		drm_err(&dev_priv->drm,  in gm45_get_cdclk()
417 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,  in hsw_get_cdclk()  argument
420 	u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);  in hsw_get_cdclk()
425 	else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)  in hsw_get_cdclk()
429 	else if (IS_HSW_ULT(dev_priv))  in hsw_get_cdclk()
435 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)  in vlv_calc_cdclk()  argument
437 	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?  in vlv_calc_cdclk()
445 	if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)  in vlv_calc_cdclk()
455 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)  in vlv_calc_voltage_level()  argument
457 	if (IS_VALLEYVIEW(dev_priv)) {  in vlv_calc_voltage_level()
470 		return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;  in vlv_calc_voltage_level()
474 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,  in vlv_get_cdclk()  argument
479 	vlv_iosf_sb_get(dev_priv,  in vlv_get_cdclk()
482 	cdclk_config->vco = vlv_get_hpll_vco(dev_priv);  in vlv_get_cdclk()
483 	cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",  in vlv_get_cdclk()
487 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);  in vlv_get_cdclk()
489 	vlv_iosf_sb_put(dev_priv,  in vlv_get_cdclk()
492 	if (IS_VALLEYVIEW(dev_priv))  in vlv_get_cdclk()
500 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)  in vlv_program_pfi_credits()  argument
504 	if (IS_CHERRYVIEW(dev_priv))  in vlv_program_pfi_credits()
509 	if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {  in vlv_program_pfi_credits()
511 		if (IS_CHERRYVIEW(dev_priv))  in vlv_program_pfi_credits()
523 	intel_de_write(dev_priv, GCI_CONTROL,  in vlv_program_pfi_credits()
526 	intel_de_write(dev_priv, GCI_CONTROL,  in vlv_program_pfi_credits()
533 	drm_WARN_ON(&dev_priv->drm,  in vlv_program_pfi_credits()
534 		    intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);  in vlv_program_pfi_credits()
537 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,  in vlv_set_cdclk()  argument
563 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);  in vlv_set_cdclk()
565 	vlv_iosf_sb_get(dev_priv,  in vlv_set_cdclk()
570 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);  in vlv_set_cdclk()
573 	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);  in vlv_set_cdclk()
574 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &  in vlv_set_cdclk()
577 		drm_err(&dev_priv->drm,  in vlv_set_cdclk()
584 		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,  in vlv_set_cdclk()
588 		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);  in vlv_set_cdclk()
591 		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);  in vlv_set_cdclk()
593 		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &  in vlv_set_cdclk()
596 			drm_err(&dev_priv->drm,  in vlv_set_cdclk()
601 	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);  in vlv_set_cdclk()
612 	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);  in vlv_set_cdclk()
614 	vlv_iosf_sb_put(dev_priv,  in vlv_set_cdclk()
619 	intel_update_cdclk(dev_priv);  in vlv_set_cdclk()
621 	vlv_program_pfi_credits(dev_priv);  in vlv_set_cdclk()
623 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);  in vlv_set_cdclk()
626 static void chv_set_cdclk(struct drm_i915_private *dev_priv,  in chv_set_cdclk()  argument
651 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);  in chv_set_cdclk()
653 	vlv_punit_get(dev_priv);  in chv_set_cdclk()
654 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);  in chv_set_cdclk()
657 	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);  in chv_set_cdclk()
658 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &  in chv_set_cdclk()
661 		drm_err(&dev_priv->drm,  in chv_set_cdclk()
665 	vlv_punit_put(dev_priv);  in chv_set_cdclk()
667 	intel_update_cdclk(dev_priv);  in chv_set_cdclk()
669 	vlv_program_pfi_credits(dev_priv);  in chv_set_cdclk()
671 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);  in chv_set_cdclk()
701 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,  in bdw_get_cdclk()  argument
704 	u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);  in bdw_get_cdclk()
709 	else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)  in bdw_get_cdclk()
745 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,  in bdw_set_cdclk()  argument
752 	if (drm_WARN(&dev_priv->drm,  in bdw_set_cdclk()
753 		     (intel_de_read(dev_priv, LCPLL_CTL) &  in bdw_set_cdclk()
761 	ret = sandybridge_pcode_write(dev_priv,  in bdw_set_cdclk()
764 		drm_err(&dev_priv->drm,  in bdw_set_cdclk()
769 	intel_de_rmw(dev_priv, LCPLL_CTL,  in bdw_set_cdclk()
776 	if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &  in bdw_set_cdclk()
778 		drm_err(&dev_priv->drm, "Switching to FCLK failed\n");  in bdw_set_cdclk()
780 	intel_de_rmw(dev_priv, LCPLL_CTL,  in bdw_set_cdclk()
783 	intel_de_rmw(dev_priv, LCPLL_CTL,  in bdw_set_cdclk()
786 	if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &  in bdw_set_cdclk()
788 		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");  in bdw_set_cdclk()
790 	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,  in bdw_set_cdclk()
793 	intel_de_write(dev_priv, CDCLK_FREQ,  in bdw_set_cdclk()
796 	intel_update_cdclk(dev_priv);  in bdw_set_cdclk()
834 static void skl_dpll0_update(struct drm_i915_private *dev_priv,  in skl_dpll0_update()  argument
842 	val = intel_de_read(dev_priv, LCPLL1_CTL);  in skl_dpll0_update()
846 	if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))  in skl_dpll0_update()
849 	val = intel_de_read(dev_priv, DPLL_CTRL1);  in skl_dpll0_update()
851 	if (drm_WARN_ON(&dev_priv->drm,  in skl_dpll0_update()
875 static void skl_get_cdclk(struct drm_i915_private *dev_priv,  in skl_get_cdclk()  argument
880 	skl_dpll0_update(dev_priv, cdclk_config);  in skl_get_cdclk()
887 	cdctl = intel_de_read(dev_priv, CDCLK_CTL);  in skl_get_cdclk()
942 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,  in skl_set_preferred_cdclk_vco()  argument
945 	bool changed = dev_priv->skl_preferred_vco_freq != vco;  in skl_set_preferred_cdclk_vco()
947 	dev_priv->skl_preferred_vco_freq = vco;  in skl_set_preferred_cdclk_vco()
950 		intel_update_max_cdclk(dev_priv);  in skl_set_preferred_cdclk_vco()
953 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)  in skl_dpll0_link_rate()  argument
955 	drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);  in skl_dpll0_link_rate()
972 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)  in skl_dpll0_enable()  argument
974 	intel_de_rmw(dev_priv, DPLL_CTRL1,  in skl_dpll0_enable()
979 		     skl_dpll0_link_rate(dev_priv, vco));  in skl_dpll0_enable()
980 	intel_de_posting_read(dev_priv, DPLL_CTRL1);  in skl_dpll0_enable()
982 	intel_de_rmw(dev_priv, LCPLL1_CTL,  in skl_dpll0_enable()
985 	if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))  in skl_dpll0_enable()
986 		drm_err(&dev_priv->drm, "DPLL0 not locked\n");  in skl_dpll0_enable()
988 	dev_priv->cdclk.hw.vco = vco;  in skl_dpll0_enable()
991 	skl_set_preferred_cdclk_vco(dev_priv, vco);  in skl_dpll0_enable()
994 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)  in skl_dpll0_disable()  argument
996 	intel_de_rmw(dev_priv, LCPLL1_CTL,  in skl_dpll0_disable()
999 	if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))  in skl_dpll0_disable()
1000 		drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");  in skl_dpll0_disable()
1002 	dev_priv->cdclk.hw.vco = 0;  in skl_dpll0_disable()
1005 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,  in skl_cdclk_freq_sel()  argument
1010 		drm_WARN_ON(&dev_priv->drm,  in skl_cdclk_freq_sel()
1011 			    cdclk != dev_priv->cdclk.hw.bypass);  in skl_cdclk_freq_sel()
1012 		drm_WARN_ON(&dev_priv->drm, vco != 0);  in skl_cdclk_freq_sel()
1028 static void skl_set_cdclk(struct drm_i915_private *dev_priv,  in skl_set_cdclk()  argument
1045 	drm_WARN_ON_ONCE(&dev_priv->drm,  in skl_set_cdclk()
1046 			 IS_SKYLAKE(dev_priv) && vco == 8640000);  in skl_set_cdclk()
1048 	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,  in skl_set_cdclk()
1053 		drm_err(&dev_priv->drm,  in skl_set_cdclk()
1058 	freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);  in skl_set_cdclk()
1060 	if (dev_priv->cdclk.hw.vco != 0 &&  in skl_set_cdclk()
1061 	    dev_priv->cdclk.hw.vco != vco)  in skl_set_cdclk()
1062 		skl_dpll0_disable(dev_priv);  in skl_set_cdclk()
1064 	cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);  in skl_set_cdclk()
1066 	if (dev_priv->cdclk.hw.vco != vco) {  in skl_set_cdclk()
1070 		intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);  in skl_set_cdclk()
1075 	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);  in skl_set_cdclk()
1076 	intel_de_posting_read(dev_priv, CDCLK_CTL);  in skl_set_cdclk()
1078 	if (dev_priv->cdclk.hw.vco != vco)  in skl_set_cdclk()
1079 		skl_dpll0_enable(dev_priv, vco);  in skl_set_cdclk()
1083 	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);  in skl_set_cdclk()
1086 	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);  in skl_set_cdclk()
1090 	intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);  in skl_set_cdclk()
1091 	intel_de_posting_read(dev_priv, CDCLK_CTL);  in skl_set_cdclk()
1094 	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,  in skl_set_cdclk()
1097 	intel_update_cdclk(dev_priv);  in skl_set_cdclk()
1100 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)  in skl_sanitize_cdclk()  argument
1109 	if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)  in skl_sanitize_cdclk()
1112 	intel_update_cdclk(dev_priv);  in skl_sanitize_cdclk()
1113 	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");  in skl_sanitize_cdclk()
1116 	if (dev_priv->cdclk.hw.vco == 0 ||  in skl_sanitize_cdclk()
1117 	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)  in skl_sanitize_cdclk()
1126 	cdctl = intel_de_read(dev_priv, CDCLK_CTL);  in skl_sanitize_cdclk()
1128 		skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);  in skl_sanitize_cdclk()
1134 	drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");  in skl_sanitize_cdclk()
1137 	dev_priv->cdclk.hw.cdclk = 0;  in skl_sanitize_cdclk()
1139 	dev_priv->cdclk.hw.vco = -1;  in skl_sanitize_cdclk()
1142 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)  in skl_cdclk_init_hw()  argument
1146 	skl_sanitize_cdclk(dev_priv);  in skl_cdclk_init_hw()
1148 	if (dev_priv->cdclk.hw.cdclk != 0 &&  in skl_cdclk_init_hw()
1149 	    dev_priv->cdclk.hw.vco != 0) {  in skl_cdclk_init_hw()
1154 		if (dev_priv->skl_preferred_vco_freq == 0)  in skl_cdclk_init_hw()
1155 			skl_set_preferred_cdclk_vco(dev_priv,  in skl_cdclk_init_hw()
1156 						    dev_priv->cdclk.hw.vco);  in skl_cdclk_init_hw()
1160 	cdclk_config = dev_priv->cdclk.hw;  in skl_cdclk_init_hw()
1162 	cdclk_config.vco = dev_priv->skl_preferred_vco_freq;  in skl_cdclk_init_hw()
1168 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);  in skl_cdclk_init_hw()
1171 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)  in skl_cdclk_uninit_hw()  argument
1173 	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;  in skl_cdclk_uninit_hw()
1179 	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);  in skl_cdclk_uninit_hw()
1292 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)  in bxt_calc_cdclk()  argument
1294 	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;  in bxt_calc_cdclk()
1298 		if (table[i].refclk == dev_priv->cdclk.hw.ref &&  in bxt_calc_cdclk()
1302 	drm_WARN(&dev_priv->drm, 1,  in bxt_calc_cdclk()
1304 		 min_cdclk, dev_priv->cdclk.hw.ref);  in bxt_calc_cdclk()
1308 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)  in bxt_calc_cdclk_pll_vco()  argument
1310 	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;  in bxt_calc_cdclk_pll_vco()
1313 	if (cdclk == dev_priv->cdclk.hw.bypass)  in bxt_calc_cdclk_pll_vco()
1317 		if (table[i].refclk == dev_priv->cdclk.hw.ref &&  in bxt_calc_cdclk_pll_vco()
1319 			return dev_priv->cdclk.hw.ref * table[i].ratio;  in bxt_calc_cdclk_pll_vco()
1321 	drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",  in bxt_calc_cdclk_pll_vco()
1322 		 cdclk, dev_priv->cdclk.hw.ref);  in bxt_calc_cdclk_pll_vco()
1365 static void icl_readout_refclk(struct drm_i915_private *dev_priv,  in icl_readout_refclk()  argument
1368 	u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;  in icl_readout_refclk()
1386 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,  in bxt_de_pll_readout()  argument
1391 	if (IS_DG2(dev_priv))  in bxt_de_pll_readout()
1393 	else if (DISPLAY_VER(dev_priv) >= 11)  in bxt_de_pll_readout()
1394 		icl_readout_refclk(dev_priv, cdclk_config);  in bxt_de_pll_readout()
1398 	val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);  in bxt_de_pll_readout()
1413 	if (DISPLAY_VER(dev_priv) >= 11)  in bxt_de_pll_readout()
1416 		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;  in bxt_de_pll_readout()
1421 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,  in bxt_get_cdclk()  argument
1427 	bxt_de_pll_readout(dev_priv, cdclk_config);  in bxt_get_cdclk()
1429 	if (DISPLAY_VER(dev_priv) >= 12)  in bxt_get_cdclk()
1431 	else if (DISPLAY_VER(dev_priv) >= 11)  in bxt_get_cdclk()
1441 	divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;  in bxt_get_cdclk()
1469 		dev_priv->display.calc_voltage_level(cdclk_config->cdclk);  in bxt_get_cdclk()
1472 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)  in bxt_de_pll_disable()  argument
1474 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);  in bxt_de_pll_disable()
1477 	if (intel_de_wait_for_clear(dev_priv,  in bxt_de_pll_disable()
1479 		drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");  in bxt_de_pll_disable()
1481 	dev_priv->cdclk.hw.vco = 0;  in bxt_de_pll_disable()
1484 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)  in bxt_de_pll_enable()  argument
1486 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);  in bxt_de_pll_enable()
1488 	intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,  in bxt_de_pll_enable()
1491 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);  in bxt_de_pll_enable()
1494 	if (intel_de_wait_for_set(dev_priv,  in bxt_de_pll_enable()
1496 		drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");  in bxt_de_pll_enable()
1498 	dev_priv->cdclk.hw.vco = vco;  in bxt_de_pll_enable()
1501 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)  in icl_cdclk_pll_disable()  argument
1503 	intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,  in icl_cdclk_pll_disable()
1507 	if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))  in icl_cdclk_pll_disable()
1508 		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");  in icl_cdclk_pll_disable()
1510 	dev_priv->cdclk.hw.vco = 0;  in icl_cdclk_pll_disable()
1513 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)  in icl_cdclk_pll_enable()  argument
1515 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);  in icl_cdclk_pll_enable()
1519 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);  in icl_cdclk_pll_enable()
1522 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);  in icl_cdclk_pll_enable()
1525 	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))  in icl_cdclk_pll_enable()
1526 		drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");  in icl_cdclk_pll_enable()
1528 	dev_priv->cdclk.hw.vco = vco;  in icl_cdclk_pll_enable()
1531 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)  in adlp_cdclk_pll_crawl()  argument
1533 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);  in adlp_cdclk_pll_crawl()
1538 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);  in adlp_cdclk_pll_crawl()
1542 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);  in adlp_cdclk_pll_crawl()
1545 	if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,  in adlp_cdclk_pll_crawl()
1550 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);  in adlp_cdclk_pll_crawl()
1552 	dev_priv->cdclk.hw.vco = vco;  in adlp_cdclk_pll_crawl()
1555 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)  in bxt_cdclk_cd2x_pipe()  argument
1557 	if (DISPLAY_VER(dev_priv) >= 12) {  in bxt_cdclk_cd2x_pipe()
1562 	} else if (DISPLAY_VER(dev_priv) >= 11) {  in bxt_cdclk_cd2x_pipe()
1575 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,  in bxt_cdclk_cd2x_div_sel()  argument
1581 		drm_WARN_ON(&dev_priv->drm,  in bxt_cdclk_cd2x_div_sel()
1582 			    cdclk != dev_priv->cdclk.hw.bypass);  in bxt_cdclk_cd2x_div_sel()
1583 		drm_WARN_ON(&dev_priv->drm, vco != 0);  in bxt_cdclk_cd2x_div_sel()
1596 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,  in bxt_set_cdclk()  argument
1606 	if (DISPLAY_VER(dev_priv) >= 11)  in bxt_set_cdclk()
1607 		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,  in bxt_set_cdclk()
1616 		ret = sandybridge_pcode_write_timeout(dev_priv,  in bxt_set_cdclk()
1621 		drm_err(&dev_priv->drm,  in bxt_set_cdclk()
1627 	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {  in bxt_set_cdclk()
1628 		if (dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1629 			adlp_cdclk_pll_crawl(dev_priv, vco);  in bxt_set_cdclk()
1630 	} else if (DISPLAY_VER(dev_priv) >= 11) {  in bxt_set_cdclk()
1631 		if (dev_priv->cdclk.hw.vco != 0 &&  in bxt_set_cdclk()
1632 		    dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1633 			icl_cdclk_pll_disable(dev_priv);  in bxt_set_cdclk()
1635 		if (dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1636 			icl_cdclk_pll_enable(dev_priv, vco);  in bxt_set_cdclk()
1638 		if (dev_priv->cdclk.hw.vco != 0 &&  in bxt_set_cdclk()
1639 		    dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1640 			bxt_de_pll_disable(dev_priv);  in bxt_set_cdclk()
1642 		if (dev_priv->cdclk.hw.vco != vco)  in bxt_set_cdclk()
1643 			bxt_de_pll_enable(dev_priv, vco);  in bxt_set_cdclk()
1646 	val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) |  in bxt_set_cdclk()
1647 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |  in bxt_set_cdclk()
1654 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&  in bxt_set_cdclk()
1657 	intel_de_write(dev_priv, CDCLK_CTL, val);  in bxt_set_cdclk()
1660 		intel_wait_for_vblank(dev_priv, pipe);  in bxt_set_cdclk()
1662 	if (DISPLAY_VER(dev_priv) >= 11) {  in bxt_set_cdclk()
1663 		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,  in bxt_set_cdclk()
1672 		ret = sandybridge_pcode_write_timeout(dev_priv,  in bxt_set_cdclk()
1679 		drm_err(&dev_priv->drm,  in bxt_set_cdclk()
1685 	intel_update_cdclk(dev_priv);  in bxt_set_cdclk()
1687 	if (DISPLAY_VER(dev_priv) >= 11)  in bxt_set_cdclk()
1692 		dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;  in bxt_set_cdclk()
1695 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)  in bxt_sanitize_cdclk()  argument
1700 	intel_update_cdclk(dev_priv);  in bxt_sanitize_cdclk()
1701 	intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");  in bxt_sanitize_cdclk()
1703 	if (dev_priv->cdclk.hw.vco == 0 ||  in bxt_sanitize_cdclk()
1704 	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)  in bxt_sanitize_cdclk()
1713 	cdctl = intel_de_read(dev_priv, CDCLK_CTL);  in bxt_sanitize_cdclk()
1719 	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);  in bxt_sanitize_cdclk()
1722 	cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);  in bxt_sanitize_cdclk()
1723 	if (cdclk != dev_priv->cdclk.hw.cdclk)  in bxt_sanitize_cdclk()
1727 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);  in bxt_sanitize_cdclk()
1728 	if (vco != dev_priv->cdclk.hw.vco)  in bxt_sanitize_cdclk()
1734 	expected |= bxt_cdclk_cd2x_div_sel(dev_priv,  in bxt_sanitize_cdclk()
1735 					   dev_priv->cdclk.hw.cdclk,  in bxt_sanitize_cdclk()
1736 					   dev_priv->cdclk.hw.vco);  in bxt_sanitize_cdclk()
1742 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&  in bxt_sanitize_cdclk()
1743 	    dev_priv->cdclk.hw.cdclk >= 500000)  in bxt_sanitize_cdclk()
1751 	drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");  in bxt_sanitize_cdclk()
1754 	dev_priv->cdclk.hw.cdclk = 0;  in bxt_sanitize_cdclk()
1757 	dev_priv->cdclk.hw.vco = -1;  in bxt_sanitize_cdclk()
1760 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)  in bxt_cdclk_init_hw()  argument
1764 	bxt_sanitize_cdclk(dev_priv);  in bxt_cdclk_init_hw()
1766 	if (dev_priv->cdclk.hw.cdclk != 0 &&  in bxt_cdclk_init_hw()
1767 	    dev_priv->cdclk.hw.vco != 0)  in bxt_cdclk_init_hw()
1770 	cdclk_config = dev_priv->cdclk.hw;  in bxt_cdclk_init_hw()
1777 	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);  in bxt_cdclk_init_hw()
1778 	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);  in bxt_cdclk_init_hw()
1780 		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);  in bxt_cdclk_init_hw()
1782 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);  in bxt_cdclk_init_hw()
1785 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)  in bxt_cdclk_uninit_hw()  argument
1787 	struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;  in bxt_cdclk_uninit_hw()
1792 		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);  in bxt_cdclk_uninit_hw()
1794 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);  in bxt_cdclk_uninit_hw()
1829 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,  in intel_cdclk_can_crawl()  argument
1835 	if (!HAS_CDCLK_CRAWL(dev_priv))  in intel_cdclk_can_crawl()
1880 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,  in intel_cdclk_can_cd2x_update()  argument
1885 	if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))  in intel_cdclk_can_cd2x_update()
1926 static void intel_set_cdclk(struct drm_i915_private *dev_priv,  in intel_set_cdclk()  argument
1932 	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))  in intel_set_cdclk()
1935 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))  in intel_set_cdclk()
1940 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {  in intel_set_cdclk()
1951 	mutex_lock(&dev_priv->gmbus_mutex);  in intel_set_cdclk()
1952 	for_each_intel_dp(&dev_priv->drm, encoder) {  in intel_set_cdclk()
1956 				     &dev_priv->gmbus_mutex);  in intel_set_cdclk()
1959 	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);  in intel_set_cdclk()
1961 	for_each_intel_dp(&dev_priv->drm, encoder) {  in intel_set_cdclk()
1966 	mutex_unlock(&dev_priv->gmbus_mutex);  in intel_set_cdclk()
1968 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {  in intel_set_cdclk()
1974 	if (drm_WARN(&dev_priv->drm,  in intel_set_cdclk()
1975 		     intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),  in intel_set_cdclk()
1977 		intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");  in intel_set_cdclk()
1992 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_set_cdclk_pre_plane_update()  local
2005 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);  in intel_set_cdclk_pre_plane_update()
2007 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_pre_plane_update()
2021 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_set_cdclk_post_plane_update()  local
2034 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);  in intel_set_cdclk_post_plane_update()
2036 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_post_plane_update()
2042 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_pixel_rate_to_cdclk()  local
2045 	if (DISPLAY_VER(dev_priv) >= 10)  in intel_pixel_rate_to_cdclk()
2047 	else if (DISPLAY_VER(dev_priv) == 9 ||  in intel_pixel_rate_to_cdclk()
2048 		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))  in intel_pixel_rate_to_cdclk()
2050 	else if (IS_CHERRYVIEW(dev_priv))  in intel_pixel_rate_to_cdclk()
2061 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_planes_min_cdclk()  local
2065 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)  in intel_planes_min_cdclk()
2073 	struct drm_i915_private *dev_priv =  in intel_crtc_compute_min_cdclk()  local
2083 	if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))  in intel_crtc_compute_min_cdclk()
2095 		if (DISPLAY_VER(dev_priv) == 10) {  in intel_crtc_compute_min_cdclk()
2098 		} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {  in intel_crtc_compute_min_cdclk()
2108 	if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)  in intel_crtc_compute_min_cdclk()
2118 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in intel_crtc_compute_min_cdclk()
2127 	    IS_VALLEYVIEW(dev_priv))  in intel_crtc_compute_min_cdclk()
2136 	    IS_GEMINILAKE(dev_priv))  in intel_crtc_compute_min_cdclk()
2151 	if (IS_TIGERLAKE(dev_priv)) {  in intel_crtc_compute_min_cdclk()
2158 					dev_priv->max_cdclk_freq));  in intel_crtc_compute_min_cdclk()
2161 	if (min_cdclk > dev_priv->max_cdclk_freq) {  in intel_crtc_compute_min_cdclk()
2162 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_compute_min_cdclk()
2164 			    min_cdclk, dev_priv->max_cdclk_freq);  in intel_crtc_compute_min_cdclk()
2174 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_compute_min_cdclk()  local
2203 	for_each_pipe(dev_priv, pipe) {  in intel_compute_min_cdclk()
2231 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in bxt_compute_min_voltage_level()  local
2257 	for_each_pipe(dev_priv, pipe)  in bxt_compute_min_voltage_level()
2267 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in vlv_modeset_calc_cdclk()  local
2274 	cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);  in vlv_modeset_calc_cdclk()
2278 		vlv_calc_voltage_level(dev_priv, cdclk);  in vlv_modeset_calc_cdclk()
2281 		cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);  in vlv_modeset_calc_cdclk()
2285 			vlv_calc_voltage_level(dev_priv, cdclk);  in vlv_modeset_calc_cdclk()
2327 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in skl_dpll0_vco()  local
2334 		vco = dev_priv->skl_preferred_vco_freq;  in skl_dpll0_vco()
2399 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in bxt_modeset_calc_cdclk()  local
2410 	cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);  in bxt_modeset_calc_cdclk()
2411 	vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2417 		      dev_priv->display.calc_voltage_level(cdclk));  in bxt_modeset_calc_cdclk()
2420 		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);  in bxt_modeset_calc_cdclk()
2421 		vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);  in bxt_modeset_calc_cdclk()
2426 			dev_priv->display.calc_voltage_level(cdclk);  in bxt_modeset_calc_cdclk()
2477 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_get_cdclk_state()  local
2480 	cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);  in intel_atomic_get_cdclk_state()
2487 int intel_cdclk_init(struct drm_i915_private *dev_priv)  in intel_cdclk_init()  argument
2495 	intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,  in intel_cdclk_init()
2503 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_calc_cdclk()  local
2518 	ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);  in intel_modeset_calc_cdclk()
2543 	    intel_cdclk_can_cd2x_update(dev_priv,  in intel_modeset_calc_cdclk()
2550 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_modeset_calc_cdclk()
2560 	if (intel_cdclk_can_crawl(dev_priv,  in intel_modeset_calc_cdclk()
2563 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_calc_cdclk()
2568 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_calc_cdclk()
2578 		drm_dbg_kms(&dev_priv->drm,  in intel_modeset_calc_cdclk()
2582 	drm_dbg_kms(&dev_priv->drm,  in intel_modeset_calc_cdclk()
2586 	drm_dbg_kms(&dev_priv->drm,  in intel_modeset_calc_cdclk()
2594 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)  in intel_compute_max_dotclk()  argument
2596 	int max_cdclk_freq = dev_priv->max_cdclk_freq;  in intel_compute_max_dotclk()
2598 	if (DISPLAY_VER(dev_priv) >= 10)  in intel_compute_max_dotclk()
2600 	else if (DISPLAY_VER(dev_priv) == 9 ||  in intel_compute_max_dotclk()
2601 		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))  in intel_compute_max_dotclk()
2603 	else if (IS_CHERRYVIEW(dev_priv))  in intel_compute_max_dotclk()
2605 	else if (DISPLAY_VER(dev_priv) < 4)  in intel_compute_max_dotclk()
2619 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)  in intel_update_max_cdclk()  argument
2621 	if (IS_JSL_EHL(dev_priv)) {  in intel_update_max_cdclk()
2622 		if (dev_priv->cdclk.hw.ref == 24000)  in intel_update_max_cdclk()
2623 			dev_priv->max_cdclk_freq = 552000;  in intel_update_max_cdclk()
2625 			dev_priv->max_cdclk_freq = 556800;  in intel_update_max_cdclk()
2626 	} else if (DISPLAY_VER(dev_priv) >= 11) {  in intel_update_max_cdclk()
2627 		if (dev_priv->cdclk.hw.ref == 24000)  in intel_update_max_cdclk()
2628 			dev_priv->max_cdclk_freq = 648000;  in intel_update_max_cdclk()
2630 			dev_priv->max_cdclk_freq = 652800;  in intel_update_max_cdclk()
2631 	} else if (IS_GEMINILAKE(dev_priv)) {  in intel_update_max_cdclk()
2632 		dev_priv->max_cdclk_freq = 316800;  in intel_update_max_cdclk()
2633 	} else if (IS_BROXTON(dev_priv)) {  in intel_update_max_cdclk()
2634 		dev_priv->max_cdclk_freq = 624000;  in intel_update_max_cdclk()
2635 	} else if (DISPLAY_VER(dev_priv) == 9) {  in intel_update_max_cdclk()
2636 		u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;  in intel_update_max_cdclk()
2639 		vco = dev_priv->skl_preferred_vco_freq;  in intel_update_max_cdclk()
2640 		drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);  in intel_update_max_cdclk()
2656 		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);  in intel_update_max_cdclk()
2657 	} else if (IS_BROADWELL(dev_priv))  {  in intel_update_max_cdclk()
2664 		if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)  in intel_update_max_cdclk()
2665 			dev_priv->max_cdclk_freq = 450000;  in intel_update_max_cdclk()
2666 		else if (IS_BDW_ULX(dev_priv))  in intel_update_max_cdclk()
2667 			dev_priv->max_cdclk_freq = 450000;  in intel_update_max_cdclk()
2668 		else if (IS_BDW_ULT(dev_priv))  in intel_update_max_cdclk()
2669 			dev_priv->max_cdclk_freq = 540000;  in intel_update_max_cdclk()
2671 			dev_priv->max_cdclk_freq = 675000;  in intel_update_max_cdclk()
2672 	} else if (IS_CHERRYVIEW(dev_priv)) {  in intel_update_max_cdclk()
2673 		dev_priv->max_cdclk_freq = 320000;  in intel_update_max_cdclk()
2674 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_update_max_cdclk()
2675 		dev_priv->max_cdclk_freq = 400000;  in intel_update_max_cdclk()
2678 		dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;  in intel_update_max_cdclk()
2681 	dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);  in intel_update_max_cdclk()
2683 	drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",  in intel_update_max_cdclk()
2684 		dev_priv->max_cdclk_freq);  in intel_update_max_cdclk()
2686 	drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",  in intel_update_max_cdclk()
2687 		dev_priv->max_dotclk_freq);  in intel_update_max_cdclk()
2696 void intel_update_cdclk(struct drm_i915_private *dev_priv)  in intel_update_cdclk()  argument
2698 	dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);  in intel_update_cdclk()
2706 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_update_cdclk()
2707 		intel_de_write(dev_priv, GMBUSFREQ_VLV,  in intel_update_cdclk()
2708 			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));  in intel_update_cdclk()
2711 static int dg1_rawclk(struct drm_i915_private *dev_priv)  in dg1_rawclk()  argument
2717 	intel_de_write(dev_priv, PCH_RAWCLK_FREQ,  in dg1_rawclk()
2723 static int cnp_rawclk(struct drm_i915_private *dev_priv)  in cnp_rawclk()  argument
2728 	if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {  in cnp_rawclk()
2744 		if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in cnp_rawclk()
2748 	intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);  in cnp_rawclk()
2752 static int pch_rawclk(struct drm_i915_private *dev_priv)  in pch_rawclk()  argument
2754 	return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;  in pch_rawclk()
2757 static int vlv_hrawclk(struct drm_i915_private *dev_priv)  in vlv_hrawclk()  argument
2760 	return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",  in vlv_hrawclk()
2764 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)  in i9xx_hrawclk()  argument
2778 	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;  in i9xx_hrawclk()
2780 	if (IS_MOBILE(dev_priv)) {  in i9xx_hrawclk()
2827 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)  in intel_read_rawclk()  argument
2831 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)  in intel_read_rawclk()
2832 		freq = dg1_rawclk(dev_priv);  in intel_read_rawclk()
2833 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)  in intel_read_rawclk()
2834 		freq = cnp_rawclk(dev_priv);  in intel_read_rawclk()
2835 	else if (HAS_PCH_SPLIT(dev_priv))  in intel_read_rawclk()
2836 		freq = pch_rawclk(dev_priv);  in intel_read_rawclk()
2837 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_read_rawclk()
2838 		freq = vlv_hrawclk(dev_priv);  in intel_read_rawclk()
2839 	else if (DISPLAY_VER(dev_priv) >= 3)  in intel_read_rawclk()
2840 		freq = i9xx_hrawclk(dev_priv);  in intel_read_rawclk()
2852 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)  in intel_init_cdclk_hooks()  argument
2854 	if (IS_DG2(dev_priv)) {  in intel_init_cdclk_hooks()
2855 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2856 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2857 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2858 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;  in intel_init_cdclk_hooks()
2859 		dev_priv->cdclk.table = dg2_cdclk_table;  in intel_init_cdclk_hooks()
2860 	} else if (IS_ALDERLAKE_P(dev_priv)) {  in intel_init_cdclk_hooks()
2861 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2862 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2863 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2864 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;  in intel_init_cdclk_hooks()
2866 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))  in intel_init_cdclk_hooks()
2867 			dev_priv->cdclk.table = adlp_a_step_cdclk_table;  in intel_init_cdclk_hooks()
2869 			dev_priv->cdclk.table = adlp_cdclk_table;  in intel_init_cdclk_hooks()
2870 	} else if (IS_ROCKETLAKE(dev_priv)) {  in intel_init_cdclk_hooks()
2871 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2872 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2873 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2874 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;  in intel_init_cdclk_hooks()
2875 		dev_priv->cdclk.table = rkl_cdclk_table;  in intel_init_cdclk_hooks()
2876 	} else if (DISPLAY_VER(dev_priv) >= 12) {  in intel_init_cdclk_hooks()
2877 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2878 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2879 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2880 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;  in intel_init_cdclk_hooks()
2881 		dev_priv->cdclk.table = icl_cdclk_table;  in intel_init_cdclk_hooks()
2882 	} else if (IS_JSL_EHL(dev_priv)) {  in intel_init_cdclk_hooks()
2883 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2884 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2885 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2886 		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;  in intel_init_cdclk_hooks()
2887 		dev_priv->cdclk.table = icl_cdclk_table;  in intel_init_cdclk_hooks()
2888 	} else if (DISPLAY_VER(dev_priv) >= 11) {  in intel_init_cdclk_hooks()
2889 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2890 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2891 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2892 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;  in intel_init_cdclk_hooks()
2893 		dev_priv->cdclk.table = icl_cdclk_table;  in intel_init_cdclk_hooks()
2894 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {  in intel_init_cdclk_hooks()
2895 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2896 		dev_priv->display.set_cdclk = bxt_set_cdclk;  in intel_init_cdclk_hooks()
2897 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2898 		dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;  in intel_init_cdclk_hooks()
2899 		if (IS_GEMINILAKE(dev_priv))  in intel_init_cdclk_hooks()
2900 			dev_priv->cdclk.table = glk_cdclk_table;  in intel_init_cdclk_hooks()
2902 			dev_priv->cdclk.table = bxt_cdclk_table;  in intel_init_cdclk_hooks()
2903 	} else if (DISPLAY_VER(dev_priv) == 9) {  in intel_init_cdclk_hooks()
2904 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2905 		dev_priv->display.set_cdclk = skl_set_cdclk;  in intel_init_cdclk_hooks()
2906 		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2907 	} else if (IS_BROADWELL(dev_priv)) {  in intel_init_cdclk_hooks()
2908 		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2909 		dev_priv->display.set_cdclk = bdw_set_cdclk;  in intel_init_cdclk_hooks()
2910 		dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2911 	} else if (IS_CHERRYVIEW(dev_priv)) {  in intel_init_cdclk_hooks()
2912 		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2913 		dev_priv->display.set_cdclk = chv_set_cdclk;  in intel_init_cdclk_hooks()
2914 		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2915 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_init_cdclk_hooks()
2916 		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2917 		dev_priv->display.set_cdclk = vlv_set_cdclk;  in intel_init_cdclk_hooks()
2918 		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2920 		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;  in intel_init_cdclk_hooks()
2921 		dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;  in intel_init_cdclk_hooks()
2924 	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))  in intel_init_cdclk_hooks()
2925 		dev_priv->display.get_cdclk = bxt_get_cdclk;  in intel_init_cdclk_hooks()
2926 	else if (DISPLAY_VER(dev_priv) == 9)  in intel_init_cdclk_hooks()
2927 		dev_priv->display.get_cdclk = skl_get_cdclk;  in intel_init_cdclk_hooks()
2928 	else if (IS_BROADWELL(dev_priv))  in intel_init_cdclk_hooks()
2929 		dev_priv->display.get_cdclk = bdw_get_cdclk;  in intel_init_cdclk_hooks()
2930 	else if (IS_HASWELL(dev_priv))  in intel_init_cdclk_hooks()
2931 		dev_priv->display.get_cdclk = hsw_get_cdclk;  in intel_init_cdclk_hooks()
2932 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_init_cdclk_hooks()
2933 		dev_priv->display.get_cdclk = vlv_get_cdclk;  in intel_init_cdclk_hooks()
2934 	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))  in intel_init_cdclk_hooks()
2935 		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;  in intel_init_cdclk_hooks()
2936 	else if (IS_IRONLAKE(dev_priv))  in intel_init_cdclk_hooks()
2937 		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;  in intel_init_cdclk_hooks()
2938 	else if (IS_GM45(dev_priv))  in intel_init_cdclk_hooks()
2939 		dev_priv->display.get_cdclk = gm45_get_cdclk;  in intel_init_cdclk_hooks()
2940 	else if (IS_G45(dev_priv))  in intel_init_cdclk_hooks()
2941 		dev_priv->display.get_cdclk = g33_get_cdclk;  in intel_init_cdclk_hooks()
2942 	else if (IS_I965GM(dev_priv))  in intel_init_cdclk_hooks()
2943 		dev_priv->display.get_cdclk = i965gm_get_cdclk;  in intel_init_cdclk_hooks()
2944 	else if (IS_I965G(dev_priv))  in intel_init_cdclk_hooks()
2945 		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;  in intel_init_cdclk_hooks()
2946 	else if (IS_PINEVIEW(dev_priv))  in intel_init_cdclk_hooks()
2947 		dev_priv->display.get_cdclk = pnv_get_cdclk;  in intel_init_cdclk_hooks()
2948 	else if (IS_G33(dev_priv))  in intel_init_cdclk_hooks()
2949 		dev_priv->display.get_cdclk = g33_get_cdclk;  in intel_init_cdclk_hooks()
2950 	else if (IS_I945GM(dev_priv))  in intel_init_cdclk_hooks()
2951 		dev_priv->display.get_cdclk = i945gm_get_cdclk;  in intel_init_cdclk_hooks()
2952 	else if (IS_I945G(dev_priv))  in intel_init_cdclk_hooks()
2953 		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;  in intel_init_cdclk_hooks()
2954 	else if (IS_I915GM(dev_priv))  in intel_init_cdclk_hooks()
2955 		dev_priv->display.get_cdclk = i915gm_get_cdclk;  in intel_init_cdclk_hooks()
2956 	else if (IS_I915G(dev_priv))  in intel_init_cdclk_hooks()
2957 		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;  in intel_init_cdclk_hooks()
2958 	else if (IS_I865G(dev_priv))  in intel_init_cdclk_hooks()
2959 		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;  in intel_init_cdclk_hooks()
2960 	else if (IS_I85X(dev_priv))  in intel_init_cdclk_hooks()
2961 		dev_priv->display.get_cdclk = i85x_get_cdclk;  in intel_init_cdclk_hooks()
2962 	else if (IS_I845G(dev_priv))  in intel_init_cdclk_hooks()
2963 		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;  in intel_init_cdclk_hooks()
2964 	else if (IS_I830(dev_priv))  in intel_init_cdclk_hooks()
2965 		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;  in intel_init_cdclk_hooks()
2967 	if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,  in intel_init_cdclk_hooks()
2969 		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;  in intel_init_cdclk_hooks()