| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 167 .clock_limits = {
1047 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1048 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1574 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz; in construct_low_pstate_lvl()
1575 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz; in construct_low_pstate_lvl()
1576 …low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_… in construct_low_pstate_lvl()
1577 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; in construct_low_pstate_lvl()
1578 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz; in construct_low_pstate_lvl()
1579 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz; in construct_low_pstate_lvl()
1580 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; in construct_low_pstate_lvl()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 169 .clock_limits = {
1549 …ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_m… in set_wm_ranges()
1550 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; in set_wm_ranges()
1575 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn301_update_bw_bounding_box() local
1589 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()
1595 clock_limits[i].state = i; in dcn301_update_bw_bounding_box()
1596 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
1597 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_update_bw_bounding_box()
1598 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn301_update_bw_bounding_box()
1599 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 154 .clock_limits = {
1316 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1318 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; in dcn302_update_bw_bounding_box()
1320 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_update_bw_bounding_box()
1322 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_update_bw_bounding_box()
1392 dcn3_02_soc.clock_limits[i].state = i; in dcn302_update_bw_bounding_box()
1393 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_update_bw_bounding_box()
1394 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn302_update_bw_bounding_box()
1395 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn302_update_bw_bounding_box()
1398 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn302_update_bw_bounding_box()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 136 .clock_limits = {
1250 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1252 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; in dcn303_update_bw_bounding_box()
1254 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; in dcn303_update_bw_bounding_box()
1256 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; in dcn303_update_bw_bounding_box()
1324 dcn3_03_soc.clock_limits[i].state = i; in dcn303_update_bw_bounding_box()
1325 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_update_bw_bounding_box()
1326 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn303_update_bw_bounding_box()
1327 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn303_update_bw_bounding_box()
1330 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn303_update_bw_bounding_box()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 232 .clock_limits = {
343 .clock_limits = {
2962 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()
2963 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()
2985 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()
2986 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn20_calculate_wm()
2991 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; in dcn20_calculate_wm()
2992 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; in dcn20_calculate_wm()
3005 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()
3006 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; in dcn20_calculate_wm()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 170 .clock_limits = {
1665 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1674 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1763 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1764 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1795 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn31_update_bw_bounding_box() local
1820 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
1826 clock_limits[i].state = i; in dcn31_update_bw_bounding_box()
1829 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
1830 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.c | 261 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()
264 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
265 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
266 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
267 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
279 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
280 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
281 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
282 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
283 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()
[all …]
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| D | display_mode_structs.h | 73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 172 .clock_limits = {
2138 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2147 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2253 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2254 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2415 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2417 max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_update_bw_bounding_box()
2419 max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_update_bw_bounding_box()
2421 max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_update_bw_bounding_box()
2493 dcn3_0_soc.clock_limits[i].state = i; in dcn30_update_bw_bounding_box()
[all …]
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| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_mode_vba_20.c | 1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| D | display_mode_vba_20v2.c | 1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_mode_vba_21.c | 1642 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_mode_vba_30.c | 2056 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /Linux-v5.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_mode_vba_31.c | 2239 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
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