Searched refs:SEC_CONTROL_REG (Results 1 – 1 of 1) sorted by relevance
62 #define SEC_CONTROL_REG 0x301200 macro326 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()335 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()384 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()386 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()402 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()404 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()427 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()508 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()[all …]
