Lines Matching refs:SEC_CONTROL_REG
62 #define SEC_CONTROL_REG 0x301200 macro
326 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
335 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
384 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
386 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
402 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
404 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
427 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
508 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
520 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
818 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
819 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
820 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()