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Searched refs:REG_FIELD_PREP (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_snps_phy.c47 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, in intel_snps_phy_update_psr_power_state()
55 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),
58 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) |
59 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6),
62 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) |
63 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12),
66 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) |
67 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19),
70 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39),
73 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) |
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Dintel_lvds.c215 …REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps-… in intel_lvds_pps_init_hw()
218 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, … in intel_lvds_pps_init_hw()
221 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_M… in intel_lvds_pps_init_hw()
Dintel_pps.c1291 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1292 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1293 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1294 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1327 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_… in pps_init_registers()
1333 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in pps_init_registers()
Dintel_bw.c763 allowed_points |= REG_FIELD_PREP(ADLS_QGV_PT_MASK, BIT(i)); in intel_bw_atomic_check()
773 allowed_points |= REG_FIELD_PREP(ADLS_PSF_PT_MASK, BIT(i)); in intel_bw_atomic_check()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_reg.h162 #define REG_FIELD_PREP(__mask, __val) \ macro
2037 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MAS…
2963 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
2964 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
2966 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
3282 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3287 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3289 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
3368 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
3369 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
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Dintel_pm.c5893 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); in skl_write_wm_level()
/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.c127 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); in gen11_enable_guc_interrupts()