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Searched refs:REG_FIELD_GET (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c98 REG_FIELD_GET(GS_MIA_IN_RESET, status), in guc_wait_ucode()
99 REG_FIELD_GET(GS_BOOTROM_MASK, status), in guc_wait_ucode()
100 REG_FIELD_GET(GS_UKERNEL_MASK, status), in guc_wait_ucode()
101 REG_FIELD_GET(GS_MIA_MASK, status), in guc_wait_ucode()
102 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); in guc_wait_ucode()
Dintel_guc_slpc.c278 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, in slpc_decode_min_freq()
289 return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, in slpc_decode_max_freq()
519 slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) * in slpc_get_rp_values()
521 slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) * in slpc_get_rp_values()
523 slpc->min_freq = REG_FIELD_GET(RPN_CAP_MASK, rp_state_cap) * in slpc_get_rp_values()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_color.c412 entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); in i9xx_lut_8_pack()
413 entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); in i9xx_lut_8_pack()
414 entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); in i9xx_lut_8_pack()
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | in i965_lut_10p6_pack()
436 REG_FIELD_GET(PALETTE_RED_MASK, ldw); in i965_lut_10p6_pack()
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | in i965_lut_10p6_pack()
438 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); in i965_lut_10p6_pack()
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | in i965_lut_10p6_pack()
440 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); in i965_lut_10p6_pack()
458 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); in ilk_lut_10_pack()
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Dintel_snps_phy.c800 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; in intel_mpllb_calc_port_clock()
802 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
805 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
806 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); in intel_mpllb_calc_port_clock()
807 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
810 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; in intel_mpllb_calc_port_clock()
812 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); in intel_mpllb_calc_port_clock()
Dintel_lvds.c162 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
163 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
164 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
172 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
Dintel_bw.c40 dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); in dg1_mchbar_read_qgv_point_info()
55 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
56 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
59 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
60 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
Dintel_vrr.c223 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); in intel_vrr_get_config()
227 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); in intel_vrr_get_config()
Dintel_pps.c1116 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1117 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1118 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1119 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1126 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1128 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
Dintel_ddi.c2298 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
3450 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); in bdw_transcoder_master_readout()
3457 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); in bdw_transcoder_master_readout()
3594 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); in intel_ddi_read_func_ctl()
Dintel_dpll_mgr.c3151 return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state); in intel_get_hti_plls()
Dintel_display.c6468 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); in hsw_get_pipe_config()
6471 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); in hsw_get_pipe_config()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_pm.c6539 level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); in skl_wm_level_from_reg_val()
Di915_reg.h179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) macro