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Searched refs:PIPECONF (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Ddisplay.c62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= in emulate_monitor_status_change()
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE; in emulate_monitor_status_change()
505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c2290 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2291 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2292 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2293 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dicl_dsi.c1061 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
1063 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
1066 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder()
1308 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1310 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1313 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder()
1743 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
Dintel_fdi.c704 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
774 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
803 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
Dintel_display.c455 i915_reg_t reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
641 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in assert_pipe()
818 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_enable_pch_transcoder()
872 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
984 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1023 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
2597 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ilk_pch_enable()
4865 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
4867 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
4937 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
[all …]
Dintel_color.c480 val = intel_de_read(dev_priv, PIPECONF(pipe)); in i9xx_color_commit()
483 intel_de_write(dev_priv, PIPECONF(pipe), val); in i9xx_color_commit()
493 val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_color_commit()
496 intel_de_write(dev_priv, PIPECONF(pipe), val); in ilk_color_commit()
Dintel_dp.c3273 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_disable()
3281 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_disable()
3301 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_enable()
3309 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_enable()
4792 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
Dintel_crt.c701 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
Dintel_display_power.c1262 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1264 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1278 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1279 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
Dvlv_dsi.c1058 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
/Linux-v5.15/drivers/gpu/drm/i915/
Di915_reg.h6185 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro