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Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 34) sorted by relevance

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/Linux-v5.15/drivers/mmc/host/
Dsdhci-of-arasan.c642 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()
711 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()
771 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()
838 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()
910 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1107 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
Ddw_mmc-hi3798cv200.c39 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
Dsdhci-pxav3.c268 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()
281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
Dsdhci-xenon.c214 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()
369 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
Dsdhci-xenon-phy.c620 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()
754 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
Drtsx_pci_sdmmc.c1028 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1109 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
1329 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()
1344 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
Dsdhci-brcmstb.c89 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
Dsdhci-pci-arasan.c284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
Dsdhci-st.c291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
Dsdhci-esdhc-imx.c1009 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1119 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()
1244 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
Dsdhci-of-dwcmshc.c149 else if ((timing == MMC_TIMING_UHS_DDR50) || in dwcmshc_set_uhs_signaling()
Dmmci_stm32_sdmmc.c200 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
Ddw_mmc-exynos.c320 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
Dsdhci-omap.c778 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1022 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
Dusdhi6rol0.c750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()
853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()
860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
Dowl-mmc.c523 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
Dsdhci-sprd.c331 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
Dsunxi-mmc.c740 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
890 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
Drtsx_usb_sdmmc.c1061 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1127 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
Dsdhci_am654.c126 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
Dsdhci.c1833 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()
2239 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()
2314 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()
2379 (ios->timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_ios()
2834 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
/Linux-v5.15/include/linux/mmc/
Dhost.h60 #define MMC_TIMING_UHS_DDR50 7 macro
604 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
/Linux-v5.15/drivers/mmc/core/
Ddebugfs.c141 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
Dsd.c488 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
660 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
671 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
Dhost.c248 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()

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