Searched refs:IS_DG1 (Results 1 – 17 of 17) sorted by relevance
140 IS_DG1(i915)) in has_phy_misc()207 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in phy_is_master()385 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { in icl_combo_phys_uninit()
700 } else if (IS_DG1(dev_priv)) { in intel_dmc_ucode_init()
166 if (IS_DG1(i915)) in intel_combo_pll_enable_reg()3189 } else if (IS_DG1(dev_priv)) { in icl_get_combo_phy_dpll()3500 } else if (IS_DG1(dev_priv)) { in icl_pll_get_hw_state()3559 } else if (IS_DG1(dev_priv)) { in icl_dpll_write()4103 else if (IS_DG1(dev_priv)) in intel_shared_dpll_init()
166 if (IS_DG1(dev_priv)) in icl_get_qgv_points()
1778 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) in dvo_port_to_port()2897 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) in intel_bios_port_aux_ch()2907 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) in intel_bios_port_aux_ch()
1600 } else if (IS_DG1(i915)) { in intel_ddi_buf_trans_init()
4987 if (IS_DG1(dev_priv)) in get_allowed_dc_mask()5133 } else if (IS_DG1(dev_priv)) { in intel_power_domains_init()5737 if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) in tgl_bw_buddy_init()
1912 if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || in gen12_plane_supports_mc_ccs()
4576 } else if (IS_DG1(dev_priv)) { in intel_ddi_init()4624 else if (IS_DG1(dev_priv)) in intel_ddi_init()
3765 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in intel_phy_is_combo()3812 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) in intel_port_to_phy()11500 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { in intel_setup_outputs()
659 if (IS_DG1(i915)) in __intel_engine_init_ctx_wa()1144 if (IS_DG1(i915)) in dg1_gt_workarounds_init()1151 if (IS_DG1(i915)) in dg1_gt_workarounds_init()1167 else if (IS_DG1(i915)) in gt_init_workarounds()1558 if (IS_DG1(i915)) in intel_engine_init_whitelist()1633 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || in rcs_engine_wa_init()1690 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || in rcs_engine_wa_init()
343 if (IS_DG1(i915)) { in get_mocs_settings()
146 } else if (IS_DG1(i915)) { in intel_step_init()
208 if (IS_DG1(dev_priv)) { in intel_detect_pch()
1442 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) macro1539 (IS_DG1(p) && IS_GT_STEP(p, since, until))1541 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
7487 IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) in gen12lp_init_clock_gating()7952 else if (IS_DG1(dev_priv)) in intel_init_clock_gating_hooks()
38 if (IS_DG1(i915) || IS_ALDERLAKE_S(i915)) { in uc_expand_default_options()