Searched refs:DCFCLKState (Results 1 – 5 of 5) sorted by relevance
456 double DCFCLKState[][2]);4738 v->DCFCLKState[i][j] = v->DCFCLKPerState[i]; in dml30_ModeSupportAndSystemConfigurationFull()4802 v->DCFCLKState); in dml30_ModeSupportAndSystemConfigurationFull()4808 if (v->DCFCLKState[i][j] < mode_lib->soc.min_dcfclk) { in dml30_ModeSupportAndSystemConfigurationFull()4809 v->DCFCLKState[i][j] = mode_lib->soc.min_dcfclk; in dml30_ModeSupportAndSystemConfigurationFull()4819 v->ReturnBusWidth * v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()4837 …> (v->RoundTripPingLatencyCycles + 32) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerSt… in dml30_ModeSupportAndSystemConfigurationFull()4896 v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()5185 v->DCFCLKState[i][j], in dml30_ModeSupportAndSystemConfigurationFull()5339 v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine]; in dml30_ModeSupportAndSystemConfigurationFull()[all …]
480 double DCFCLKState[][2]);2124 v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],5082 v->DCFCLKState[i][j] = v->DCFCLKPerState[i];5144 v->DCFCLKState);5150 v->ReturnBusWidth * v->DCFCLKState[i][j],5172 …> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBy…5191 v->ReturnBusWidth * v->DCFCLKState[i][j],5245 v->ReturnBusWidth * v->DCFCLKState[i][j],5256 v->DCFCLKState[i][j],5568 v->DCFCLKState[i][j],[all …]
421 double DCFCLKState[DC__VOLTAGE_STATES][2]; member
1658 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
2129 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_calculate_wm_and_dlg_fp()
