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Searched refs:se_num (Results 1 – 18 of 18) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
Dnv.c218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
224 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
229 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
236 bool indexed, u32 se_num, in nv_get_register_value() argument
240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
263 se_num, sh_num, reg_offset); in nv_read_register()
Dsoc15.c342 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
348 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
349 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
353 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
360 bool indexed, u32 se_num, in soc15_get_register_value() argument
364 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
374 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
390 se_num, sh_num, reg_offset); in soc15_read_register()
Dvi.c531 bool indexed, u32 se_num, in vi_get_register_value() argument
536 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in vi_get_register_value()
551 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
552 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
556 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
626 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
638 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
Dcik.c1047 bool indexed, u32 se_num, in cik_get_register_value() argument
1052 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in cik_get_register_value()
1067 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1068 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1072 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1142 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1154 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
Dgfx_v9_4.c93 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_select_se_sh() argument
105 if (se_num == 0xffffffff) in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
883 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_query_ras_error_count()
918 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_reset_ras_error_count()
1009 for (i = 0; i < gfx_v9_4_rdrsp_status_regs.se_num; i++) { in gfx_v9_4_query_ras_error_status()
Dsoc15.h58 uint32_t se_num; member
Dsi.c1055 bool indexed, u32 se_num, in si_get_register_value() argument
1060 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in si_get_register_value()
1073 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1074 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1078 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1129 static int si_read_register(struct amdgpu_device *adev, u32 se_num, in si_read_register() argument
1141 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
Damdgpu_kms.c676 unsigned se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
685 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
686 se_num = 0xffffffff; in amdgpu_info_ioctl()
687 else if (se_num >= AMDGPU_GFX_MAX_SE) in amdgpu_info_ioctl()
704 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
Damdgpu_gfx.h204 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
Dgfx_v6_0.c1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1314 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
Dgfx_v7_0.c1589 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh() argument
1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1601 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1606 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1609 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
Damdgpu.h590 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
Dgfx_v9_0.c2410 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2420 if (se_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2423 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
6556 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_reset_ras_error_count()
6618 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { in gfx_v9_0_query_ras_error_count()
Dgfx_v8_0.c3431 u32 se_num, u32 sh_num, u32 instance) in gfx_v8_0_select_se_sh() argument
3440 if (se_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3443 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
Dgfx_v10_0.c3203 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4543 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v10_0_select_se_sh() argument
4555 if (se_num == 0xffffffff) in gfx_v10_0_select_se_sh()
4559 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
/Linux-v5.10/drivers/gpu/drm/radeon/
Dsi.c2952 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2956 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2958 else if (se_num == 0xffffffff) in si_select_se_sh()
2961 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in si_select_se_sh()
2963 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
2997 u32 se_num, u32 sh_per_se, in si_setup_spi() argument
3003 for (i = 0; i < se_num; i++) { in si_setup_spi()
3044 u32 se_num, u32 sh_per_se, in si_setup_rb() argument
3052 for (i = 0; i < se_num; i++) { in si_setup_rb()
3062 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in si_setup_rb()
[all …]
Dcik.c3036 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3040 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3042 else if (se_num == 0xffffffff) in cik_select_se_sh()
3045 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); in cik_select_se_sh()
3047 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()
3112 u32 se_num, u32 sh_per_se, in cik_setup_rb() argument
3120 for (i = 0; i < se_num; i++) { in cik_setup_rb()
3133 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in cik_setup_rb()
3141 for (i = 0; i < se_num; i++) { in cik_setup_rb()