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Searched refs:reg_base (Results 1 – 25 of 333) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
[all …]
/Linux-v5.10/drivers/gpio/
Dgpio-bcm-kona.c67 void __iomem *reg_base; member
83 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
99 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
101 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
115 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
117 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
125 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
128 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
Dgpio-amdpt.c27 void __iomem *reg_base; member
40 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
48 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
63 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
65 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
89 pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in pt_gpio_probe()
90 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
92 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
96 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
97 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
[all …]
Dgpio-menz127.c34 void __iomem *reg_base; member
69 db_en = readl(priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
79 writel(db_en, priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
80 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); in men_z127_debounce()
95 od_en = readl(priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
103 writel(od_en, priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
148 men_z127_gpio->reg_base = ioremap(men_z127_gpio->mem->start, in men_z127_probe()
150 if (men_z127_gpio->reg_base == NULL) { in men_z127_probe()
158 men_z127_gpio->reg_base + MEN_Z127_PSR, in men_z127_probe()
159 men_z127_gpio->reg_base + MEN_Z127_CTRL, in men_z127_probe()
[all …]
/Linux-v5.10/arch/sh/drivers/pci/
Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
105 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
132 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
177 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
/Linux-v5.10/drivers/irqchip/
Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, in ck_set_gc() argument
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
181 writel(0x0, reg_base + GX_INTC_NMASK31_00); in gx_intc_init()
[all …]
Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/Linux-v5.10/drivers/net/ethernet/cavium/thunder/
Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/Linux-v5.10/drivers/ata/
Dahci_qoriq.c63 struct ccsr_ahci *reg_base; member
173 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
181 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
182 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
183 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
184 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
185 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
186 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
189 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
199 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
[all …]
Dahci_sunxi.c86 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) in ahci_sunxi_phy_init() argument
92 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
[all …]
/Linux-v5.10/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/Linux-v5.10/drivers/ide/
Dopti621.c30 static int reg_base; variable
41 inw(reg_base + 1); in write_reg()
42 inw(reg_base + 1); in write_reg()
43 outb(3, reg_base + 2); in write_reg()
44 outb(value, reg_base + reg); in write_reg()
45 outb(0x83, reg_base + 2); in write_reg()
57 inw(reg_base + 1); in read_reg()
58 inw(reg_base + 1); in read_reg()
59 outb(3, reg_base + 2); in read_reg()
60 ret = inb(reg_base + reg); in read_reg()
[all …]
/Linux-v5.10/drivers/remoteproc/
Dqcom_q6v5_wcss.c77 void __iomem *reg_base; member
107 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
109 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
117 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
126 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
128 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
133 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
136 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
[all …]
Dmtk_scp.c142 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
144 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
151 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
153 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
158 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); in mt8192_scp_reset_assert()
163 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); in mt8192_scp_reset_deassert()
170 scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
178 scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
185 scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); in mt8192_scp_irq_handler()
197 scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); in mt8192_scp_irq_handler()
[all …]
/Linux-v5.10/drivers/rtc/
Drtc-zynqmp.c46 void __iomem *reg_base; member
69 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); in xlnx_rtc_set_time()
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
[all …]
/Linux-v5.10/drivers/clk/samsung/
Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
53 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
74 reg_base = devm_ioremap_resource(&pdev->dev, res); in s5pv210_audss_clk_probe()
75 if (IS_ERR(reg_base)) { in s5pv210_audss_clk_probe()
77 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
120 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
131 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
135 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
138 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
Dclk-exynos-audss.c22 static void __iomem *reg_base; variable
47 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
57 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
141 reg_base = devm_ioremap_resource(dev, res); in exynos_audss_clk_probe()
142 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
143 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
189 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
200 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
204 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
208 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/Linux-v5.10/drivers/spi/
Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
294 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
299 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
303 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
312 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
317 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
350 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
443 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
459 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
/Linux-v5.10/arch/arm/mach-rockchip/
Drockchip.c29 void __iomem *reg_base; in rockchip_timer_init() local
36 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
37 if (reg_base) { in rockchip_timer_init()
38 writel(0, reg_base + 0x30); in rockchip_timer_init()
39 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
40 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
41 writel(1, reg_base + 0x30); in rockchip_timer_init()
43 iounmap(reg_base); in rockchip_timer_init()
/Linux-v5.10/drivers/net/can/
Dkvaser_pciefd.c255 void __iomem *reg_base; member
268 void __iomem *reg_base; member
329 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, in kvaser_pciefd_spi_wait_loop()
340 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); in kvaser_pciefd_spi_cmd()
341 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); in kvaser_pciefd_spi_cmd()
342 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
349 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
354 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
362 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
367 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
[all …]
/Linux-v5.10/drivers/clk/zte/
Dclk.c47 hw_cfg0 = readl_relaxed(zx_pll->reg_base); in hw_to_idx()
48 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); in hw_to_idx()
100 writel_relaxed(config->cfg0, zx_pll->reg_base); in zx_pll_set_rate()
101 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); in zx_pll_set_rate()
115 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_enable()
116 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_enable()
118 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, in zx_pll_enable()
130 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_disable()
131 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_disable()
139 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_is_enabled()
[all …]
/Linux-v5.10/arch/powerpc/boot/
Dns16550.c30 static unsigned char *reg_base; variable
35 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
41 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
42 out_8(reg_base, c); in ns16550_putc()
47 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
48 return in_8(reg_base); in ns16550_getc()
53 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
61 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) in ns16550_console_init()
66 reg_base += reg_offset; in ns16550_console_init()
/Linux-v5.10/drivers/input/serio/
Dsun4i-ps2.c85 void __iomem *reg_base; member
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/Linux-v5.10/drivers/fpga/
Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
186 priv->reg_base = reg_base; in alt_pr_register()
[all …]
/Linux-v5.10/arch/sparc/kernel/
Dsbus.c213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
223 imap += reg_base; in sbus_build_irq()
238 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
241 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
244 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
248 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
280 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
281 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
[all …]

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