46 	void __iomem		*reg_base;  member
69 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));  in xlnx_rtc_set_time()
71 	writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);  in xlnx_rtc_set_time()
81 	writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);  in xlnx_rtc_set_time()
92 	status = readl(xrtcdev->reg_base + RTC_INT_STS);  in xlnx_rtc_read_time()
99 		read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);  in xlnx_rtc_read_time()
108 		read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;  in xlnx_rtc_read_time()
119 	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);  in xlnx_rtc_read_alarm()
120 	alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;  in xlnx_rtc_read_alarm()
135 			status = readl(xrtcdev->reg_base + RTC_INT_STS);  in xlnx_rtc_alarm_irq_enable()
143 			writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);  in xlnx_rtc_alarm_irq_enable()
146 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);  in xlnx_rtc_alarm_irq_enable()
148 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);  in xlnx_rtc_alarm_irq_enable()
161 	writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));  in xlnx_rtc_set_alarm()
173 	rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);  in xlnx_init_rtc()
175 	writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);  in xlnx_init_rtc()
184 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));  in xlnx_init_rtc()
200 	status = readl(xrtcdev->reg_base + RTC_INT_STS);  in xlnx_rtc_interrupt()
206 	writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);  in xlnx_rtc_interrupt()
232 	xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);  in xlnx_rtc_probe()
233 	if (IS_ERR(xrtcdev->reg_base))  in xlnx_rtc_probe()
234 		return PTR_ERR(xrtcdev->reg_base);  in xlnx_rtc_probe()