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Searched refs:mmRLC_CNTL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/pm/inc/
Dpolaris10_pwrvirus.h49 { 0x00000000, mmRLC_CNTL },
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2456 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc()
2458 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2465 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc()
2469 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc()
2479 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2487 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
Dgfx_v7_0.c3394 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3396 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3403 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3409 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc()
3467 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3483 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
Dgfx_v8_0.c5561 rlc_setting = RREG32(mmRLC_CNTL); in gfx_v8_0_is_rlc_enabled()
5572 data = RREG32(mmRLC_CNTL); in gfx_v8_0_set_safe_mode()
5600 data = RREG32(mmRLC_CNTL); in gfx_v8_0_unset_safe_mode()
Dgfx_v10_0.c4871 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop()
4874 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop()
5265 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable()
7282 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
Dgfx_v9_0.c4704 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1136 #define mmRLC_CNTL 0x30C0 macro
Dgfx_7_0_d.h1240 #define mmRLC_CNTL 0x30c0 macro
Dgfx_7_2_d.h1253 #define mmRLC_CNTL 0x30c0 macro
Dgfx_8_0_d.h1342 #define mmRLC_CNTL 0xec00 macro
Dgfx_8_1_d.h1345 #define mmRLC_CNTL 0xec00 macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h5963 #define mmRLC_CNTL … macro
Dgc_9_1_offset.h6185 #define mmRLC_CNTL … macro
Dgc_9_2_1_offset.h6149 #define mmRLC_CNTL … macro
Dgc_10_1_0_offset.h9271 #define mmRLC_CNTL … macro
Dgc_10_3_0_offset.h9069 #define mmRLC_CNTL … macro