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Searched refs:mmGRBM_GFX_INDEX (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
[all …]
Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
159 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_set_wptr()
275 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); in vce_v3_0_start()
[all …]
Dmxgpu_vi.c48 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
78 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
125 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
133 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
139 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
169 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
268 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
Dsi.c427 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
452 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
556 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
581 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
654 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
679 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
754 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
779 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
834 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
859 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
Dsoc15_common.h110 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \
Damdgpu_amdkfd_gfx_v8.c587 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
597 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
Damdgpu_amdkfd_gfx_v7.c614 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
623 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
Dgfx_v8_0.c218 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
231 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
260 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
330 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
361 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
392 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
404 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
412 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
434 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
463 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
[all …]
Damdgpu_amdkfd_gfx_v10.c720 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); in kgd_wave_control_execute()
730 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); in kgd_wave_control_execute()
Damdgpu_amdkfd_gfx_v9.c668 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); in kgd_gfx_v9_wave_control_execute()
678 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in kgd_gfx_v9_wave_control_execute()
Damdgpu_amdkfd_gfx_v10_3.c630 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v10_3()
640 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); in wave_control_execute_v10_3()
Dgfx_v9_4.c117 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_4_select_se_sh()
927 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_4_reset_ras_error_count()
Dgfx_v9_0.c706 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
751 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; in gfx_v9_0_rlcg_wreg()
2430 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_0_select_se_sh()
6563 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_0_reset_ras_error_count()
Dgfx_v6_0.c1323 WREG32(mmGRBM_GFX_INDEX, data); in gfx_v6_0_select_se_sh()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_powertune.c923 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
938 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
974 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
983 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1035 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1046 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1085 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1094 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1144 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
Dsmu7_powertune.c976 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); in smu7_enable_didt_config()
981 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value); in smu7_enable_didt_config()
1008 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2); in smu7_enable_didt_config()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h229 #define mmGRBM_GFX_INDEX … macro
Dgc_9_0_offset.h4913 #define mmGRBM_GFX_INDEX … macro
Dgc_9_1_offset.h5143 #define mmGRBM_GFX_INDEX … macro
Dgc_9_2_1_offset.h5099 #define mmGRBM_GFX_INDEX … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h750 #define mmGRBM_GFX_INDEX 0x200B macro
Dgfx_7_0_d.h783 #define mmGRBM_GFX_INDEX 0xc200 macro
Dgfx_7_2_d.h796 #define mmGRBM_GFX_INDEX 0xc200 macro
Dgfx_8_0_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro
Dgfx_8_1_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro

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