Searched refs:mmCP_RB0_WPTR (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2116 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v6_0_cp_gfx_resume()
2149 return RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_get_wptr()
2162 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_gfx()
2163 (void)RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_set_wptr_gfx()
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| D | gfx_v7_0.c | 2628 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_cp_gfx_resume()
2663 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2670 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_gfx()
2671 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
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| D | gfx_v8_0.c | 4297 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_cp_gfx_resume()
6050 return RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_get_wptr_gfx()
6062 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6063 (void)RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_set_wptr_gfx()
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| D | gfx_v9_0.c | 3267 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
5167 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
5183 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
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| D | gfx_v10_0.c | 5912 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
7702 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
7718 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_ring_set_wptr_gfx()
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| /Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 499 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_7_0_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_7_2_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_8_0_d.h | 238 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_8_1_d.h | 239 #define mmCP_RB0_WPTR 0x3045 macro
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| /Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2420 #define mmCP_RB0_WPTR … macro
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| D | gc_9_1_offset.h | 2697 #define mmCP_RB0_WPTR … macro
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| D | gc_9_2_1_offset.h | 2635 #define mmCP_RB0_WPTR … macro
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| D | gc_10_1_0_offset.h | 4761 #define mmCP_RB0_WPTR … macro
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| D | gc_10_3_0_offset.h | 4406 #define mmCP_RB0_WPTR … macro
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