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Searched refs:mmCGTS_SM_CTRL_REG (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c79 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
210 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
Dsi.c533 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
632 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
730 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
810 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
890 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
Dgfx_v8_0.c301 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
464 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
565 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
671 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
709 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
5490 data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_get_clockgating_state()
5686 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5697 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
5728 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5732 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v6_0.c2607 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2610 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
2642 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2645 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
Dgfx_v7_0.c3658 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3670 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
3690 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3693 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h298 #define mmCGTS_SM_CTRL_REG 0x2454 macro
Dgfx_7_0_d.h1480 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_7_2_d.h1501 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_0_d.h1694 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_1_d.h1662 #define mmCGTS_SM_CTRL_REG 0xf000 macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6303 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_1_offset.h6525 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_2_1_offset.h6537 #define mmCGTS_SM_CTRL_REG … macro