Searched refs:hccr (Results 1 – 10 of 10) sorted by relevance
| /Linux-v5.10/drivers/scsi/qla2xxx/ |
| D | qla_dbg.c | 135 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); in qla27xx_dump_mpi_ram()
151 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
152 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()
158 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
159 rd_reg_dword(®->hccr); in qla27xx_dump_mpi_ram()
213 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); in qla24xx_dump_ram()
227 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
228 rd_reg_dword(®->hccr); in qla24xx_dump_ram()
234 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
235 rd_reg_dword(®->hccr); in qla24xx_dump_ram()
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| D | qla_isr.c | 188 uint16_t hccr; in qla2100_intr_handler() local
207 hccr = rd_reg_word(®->hccr); in qla2100_intr_handler()
208 if (qla2x00_check_reg16_for_disconnect(vha, hccr)) in qla2100_intr_handler()
210 if (hccr & HCCR_RISC_PAUSE) { in qla2100_intr_handler()
219 wrt_reg_word(®->hccr, HCCR_RESET_RISC); in qla2100_intr_handler()
220 rd_reg_word(®->hccr); in qla2100_intr_handler()
229 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
230 rd_reg_word(®->hccr); in qla2100_intr_handler()
254 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
255 rd_reg_word(®->hccr); in qla2100_intr_handler()
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| D | qla_init.c | 2411 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); in qla2300_pci_config()
2413 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()
2434 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); in qla2300_pci_config()
2436 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()
2599 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); in qla2x00_reset_chip()
2602 if ((rd_reg_word(®->hccr) & in qla2x00_reset_chip()
2608 rd_reg_word(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2650 wrt_reg_word(®->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
2651 rd_reg_word(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
2654 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
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| D | qla_dbg.h | 14 __be16 hccr; member
38 __be16 hccr; member
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| D | qla_mbx.c | 257 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
259 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
315 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
317 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
403 uint32_t ictrl, host_status, hccr; in qla2x00_mailbox_command() local
414 hccr = rd_reg_dword(®->isp24.hccr); in qla2x00_mailbox_command()
420 mb[7], host_status, hccr); in qla2x00_mailbox_command()
5435 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); in qla81xx_write_mpi_register()
5449 wrt_reg_dword(®->hccr, in qla81xx_write_mpi_register()
5451 rd_reg_dword(®->hccr); in qla81xx_write_mpi_register()
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| D | qla_sup.c | 2323 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); in qla2x00_suspend_hba()
2324 rd_reg_word(®->hccr); in qla2x00_suspend_hba()
2327 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
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| D | qla_fw.h | 1198 __le32 hccr; /* Host command & control register. */ member
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| D | qla_def.h | 812 __le16 hccr; /* Host command & control register. */ member
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| D | qla_iocb.c | 477 rd_reg_dword_relaxed(&ha->iobase->isp24.hccr); in qla2x00_start_iocbs()
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| D | qla_os.c | 7498 stat = rd_reg_word(®->hccr); in qla2xxx_pci_mmio_enabled()
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