Searched refs:clock_ctl (Results 1 – 3 of 3) sorted by relevance
204 static unsigned __init ar2315_sys_clk(u32 clock_ctl) in ar2315_sys_clk() argument218 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { in ar2315_sys_clk()234 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); in ar2315_sys_clk()
679 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; in jmb38x_ms_set_param() local725 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()732 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()738 clock_ctl |= CLOCK_CONTROL_50MHZ; in jmb38x_ms_set_param()745 writel(clock_ctl, host->addr + CLOCK_CONTROL); in jmb38x_ms_set_param()
6151 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write() local6153 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP); in tg3_refclk_write()6156 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME); in tg3_refclk_write()6272 u32 clock_ctl; in tg3_ptp_enable() local6285 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()6286 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK; in tg3_ptp_enable()6314 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0); in tg3_ptp_enable()6317 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl); in tg3_ptp_enable()
