| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-imx6sx.c | 185 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
186 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
187 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
188 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
189 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
190 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
191 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
506 clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); in imx6sx_clocks_init()
510 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); in imx6sx_clocks_init()
511 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); in imx6sx_clocks_init()
[all …]
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| D | clk-imx6q.c | 277 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
502 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
503 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
504 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
505 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
506 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
507 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
508 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
927 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); in imx6q_clocks_init()
929 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
[all …]
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| D | clk-imx6ul.c | 167 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
170 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
171 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
172 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
173 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
483 clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
484 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk); in imx6ul_clocks_init()
485 clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk); in imx6ul_clocks_init()
[all …]
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| D | clk-vf610.c | 236 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init()
237 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init()
238 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init()
239 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init()
240 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init()
241 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init()
242 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init()
447 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
452 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
457 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
[all …]
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| D | clk-cpu.c | 48 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate()
55 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
59 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
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| D | clk-imx6sl.c | 241 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
242 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
243 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
244 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
245 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
246 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
247 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
441 clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); in imx6sl_clocks_init()
444 clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, in imx6sl_clocks_init()
447 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, in imx6sl_clocks_init()
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| D | clk-imx5.c | 301 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init()
371 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
372 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
462 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
465 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
466 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
616 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
617 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
624 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
627 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
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| /Linux-v5.10/sound/soc/mediatek/mt8183/ |
| D | mt8183-afe-clk.c | 134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
[all …]
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| /Linux-v5.10/drivers/cpufreq/ |
| D | tegra124-cpufreq.c | 38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
44 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
49 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
142 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpufreq_suspend()
168 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpufreq_resume()
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| D | imx6q-cpufreq.c | 128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
130 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
133 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
136 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
139 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
142 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
143 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
146 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
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| D | imx-cpufreq-dt.c | 66 clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
67 clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
70 clk_set_parent(imx7ulp_clks[ARM].clk, in imx7ulp_target_intermediate()
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
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| D | mediatek-cpufreq.c | 250 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
264 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
270 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
288 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
290 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
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| D | kirkwood-cpufreq.c | 65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
68 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
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| D | loongson1-cpufreq.c | 67 clk_set_parent(policy->clk, cpufreq->osc_clk); in ls1x_cpufreq_target()
73 clk_set_parent(policy->clk, cpufreq->mux_clk); in ls1x_cpufreq_target()
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| /Linux-v5.10/sound/soc/samsung/ |
| D | smdk_spdif.c | 55 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy()
56 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy()
57 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
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| /Linux-v5.10/arch/m68k/coldfire/ |
| D | clk.c | 147 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
152 EXPORT_SYMBOL(clk_set_parent);
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| /Linux-v5.10/drivers/clk/ti/ |
| D | clk-33xx.c | 303 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
306 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
316 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
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| /Linux-v5.10/sound/soc/tegra/ |
| D | tegra_asoc_utils.c | 185 ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0); in tegra_asoc_utils_init()
198 ret = clk_set_parent(clk_out_1, clk_extern1); in tegra_asoc_utils_init()
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| /Linux-v5.10/drivers/clk/mmp/ |
| D | clk-pxa910.c | 209 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
220 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
231 clk_set_parent(clk, uart_pll); in pxa910_clk_init()
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| D | clk-mmp2.c | 249 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
260 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
271 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
282 clk_set_parent(clk, vctcxo); in mmp2_clk_init()
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| D | clk-pxa168.c | 204 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
215 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
226 clk_set_parent(clk, uart_pll); in pxa168_clk_init()
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| /Linux-v5.10/drivers/devfreq/ |
| D | imx8m-ddrc.c | 193 ret = clk_set_parent(priv->dram_core, new_dram_core_parent); in imx8m_ddrc_set_freq()
197 ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent); in imx8m_ddrc_set_freq()
203 ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent); in imx8m_ddrc_set_freq()
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| /Linux-v5.10/drivers/gpu/drm/imx/ |
| D | imx-ldb.c | 179 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
196 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
197 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
202 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
331 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()
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| /Linux-v5.10/arch/arm/mach-spear/ |
| D | spear3xx.c | 105 clk_set_parent(gpt_clk, pclk); in spear3xx_timer_init()
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| /Linux-v5.10/drivers/clk/sirf/ |
| D | clk-common.c | 414 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
419 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
424 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); in cpu_clk_set_rate()
432 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
438 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
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