Home
last modified time | relevance | path

Searched refs:amdgpu_sriov_vf (Results 1 – 25 of 63) sorted by relevance

123

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dnv.c490 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
492 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
501 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
516 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
525 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
528 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
538 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
540 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
549 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
564 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
[all …]
Damdgpu_psp.c67 if (amdgpu_sriov_vf(adev)) in psp_check_pmfw_centralized_cstate_management()
164 if (!amdgpu_sriov_vf(adev)) { in psp_sw_init()
289 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); in psp_cmd_submit_buf()
327 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
388 if (!amdgpu_sriov_vf(psp->adev) && in psp_tmr_init()
399 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_init()
412 if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12) in psp_clear_vf_fw()
446 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) in psp_tmr_load()
469 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_unload_cmd_buf()
506 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_terminate()
[all …]
Dvega10_ih.c53 if (amdgpu_sriov_vf(adev)) { in vega10_ih_enable_interrupts()
67 if (amdgpu_sriov_vf(adev)) { in vega10_ih_enable_interrupts()
83 if (amdgpu_sriov_vf(adev)) { in vega10_ih_enable_interrupts()
109 if (amdgpu_sriov_vf(adev)) { in vega10_ih_disable_interrupts()
128 if (amdgpu_sriov_vf(adev)) { in vega10_ih_disable_interrupts()
148 if (amdgpu_sriov_vf(adev)) { in vega10_ih_disable_interrupts()
240 if (amdgpu_sriov_vf(adev)) { in vega10_ih_irq_init()
288 if (amdgpu_sriov_vf(adev)) { in vega10_ih_irq_init()
315 if (amdgpu_sriov_vf(adev)) { in vega10_ih_irq_init()
519 if (amdgpu_sriov_vf(adev)) in vega10_ih_set_rptr()
Dsoc15.c697 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
730 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
750 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
755 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
761 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
775 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
787 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
797 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
803 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
809 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
[all …]
Dpsp_v3_1.c233 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
294 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
305 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
381 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
392 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
Dnavi10_ih.c97 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
128 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
173 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
193 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
301 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_irq_init()
360 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_irq_init()
386 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_irq_init()
589 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
Dathub_v1_0.c68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
93 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
Dpsp_v12_0.c270 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
322 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
333 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
400 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
412 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
Dmmhub_v1_0.c113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
161 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
212 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
303 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
314 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
360 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
379 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
530 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
555 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
Dgmc_v9_0.c546 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_process_interrupt()
578 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_process_interrupt()
648 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_set_irq_funcs()
685 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
748 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
1215 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { in gmc_v9_0_late_init()
1237 if (!amdgpu_sriov_vf(adev)) in gmc_v9_0_vram_gtt_location()
1359 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1409 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1443 if (!amdgpu_sriov_vf(adev)) { in gmc_v9_0_sw_init()
[all …]
Damdgpu_vf_error.c36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
Dsdma_v5_0.c168 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
206 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_microcode()
589 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
603 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
627 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
662 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
712 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_0_gfx_resume()
733 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
739 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
762 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
[all …]
Dpsp_v11_0.c153 if (amdgpu_sriov_vf(adev)) in psp_v11_0_init_microcode()
409 if ((!amdgpu_sriov_vf(adev)) && in psp_v11_0_ring_init()
440 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
451 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
469 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
734 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
746 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
Damdgpu_virt.c211 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
238 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
656 if (amdgpu_sriov_vf(adev)) { in amdgpu_detect_virtualization()
693 if (!amdgpu_sriov_vf(adev) || in amdgpu_virt_enable_access_debugfs()
707 if (amdgpu_sriov_vf(adev)) in amdgpu_virt_disable_access_debugfs()
715 if (amdgpu_sriov_vf(adev)) { in amdgpu_virt_get_sriov_vf_mode()
Dmmhub_v2_0.c203 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
258 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
319 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
455 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
629 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
654 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
Damdgpu_device.c1096 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1167 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
1924 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2011 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) in amdgpu_device_ip_early_init()
2070 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || in amdgpu_device_ip_hw_init_phase1()
2142 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) in amdgpu_device_fw_loading()
2198 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_init()
2210 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2262 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2519 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) in amdgpu_device_ip_fini()
[all …]
Dvi.c277 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
1317 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1329 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1339 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1373 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1617 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
1665 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
1742 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
1750 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
1762 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
[all …]
Dgmc_v10_0.c103 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
131 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
153 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
171 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
289 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
837 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1021 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
Dgfxhub_v1_0.c78 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { in gfxhub_v1_0_init_system_aperture_regs()
279 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { in gfxhub_v1_0_gart_enable()
295 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
299 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
Damdgpu_ib.c182 (amdgpu_sriov_vf(adev) && need_ctx_switch) || in amdgpu_ib_schedule()
245 !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */ in amdgpu_ib_schedule()
375 if (amdgpu_sriov_vf(adev)) { in amdgpu_ib_ring_tests()
Damdgpu_virt.h229 #define amdgpu_sriov_vf(adev) \ macro
239 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
Dgfxhub_v2_1.c212 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_init_cache_regs()
273 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_disable_identity_aperture()
353 if (amdgpu_sriov_vf(adev)) { in gfxhub_v2_1_gart_enable()
416 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_set_fault_enable_default()
Dvcn_v2_0.c72 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_early_init()
164 if (!amdgpu_sriov_vf(adev)) in vcn_v2_0_sw_init()
228 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
236 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
327 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_mc_resume()
486 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_clock_gating()
647 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_clock_gating()
701 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_static_power_gating()
750 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_static_power_gating()
1295 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_set_clockgating_state()
[all …]
Dathub_v2_0.c72 if (amdgpu_sriov_vf(adev)) in athub_v2_0_set_clockgating()
Dathub_v2_1.c71 if (amdgpu_sriov_vf(adev)) in athub_v2_1_set_clockgating()

123